View AD6620AS_7096297.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad6620 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 67 msps digital receive signal processor functional block diagram real, dual real, or complex inputs serial or parallel outputs cic filters output format complex nco p or serial control i q ?in cos external sync circuitry jtag port ii qq fir filter ad6620 features high input sample rate 67 msps single channel real 33.5 msps diversity channel real 33.5 msps single channel complex nco frequency translation worst spur better than C100 dbc tuning resolution better than 0.02 hz 2nd order cascaded integrator comb fir filter linear phase, fixed coefficients programmable decimation rates: 2, 3 . . . 16 5th order cascaded integrator comb fir filter linear phase, fixed coefficients programmable decimation rates: 1, 2, 3 . . . 32 programmable decimating ram coefficient fir filter up to 134 million taps per second 256 20-bit programmable coefficients programmable decimation rates: 1, 2, 3 . . . 32 bidirectional synchronization circuitry phase aligns ncos synchronizes data output clocks serial or parallel baseband outputs pin selectable serial or parallel serial works with sharc ? , adsp-21xx, most other dsps 16-bit parallel port, interleaved i and q outputs two separate control and configuration ports generic p port, serial port 3.3 v optimized cmos process jtag boundary scan general description the ad6620 is a digital receiver with four cascaded signal- processing elements: a frequency translator, two fixed- coef ficient decimating filters, and a programmable coefficient decimating filter. all inputs are 3.3 v lvcmos compatible. all outputs are lvcmos and 5 v ttl compatible. as adcs achieve higher sampling rates and dynamic range, it becomes increasingly attractive to accomplish the final if stage of a receiver in the digital domain. digital if processing is less expensive, easier to manufacture, more accurate, and more flexible than a comparable highly selective analog stage. the ad6620 diversity channel decimating receiver is designed to bridge the gap between high-speed adcs and general pur- pose dsps. the high resolution nco allows a single carrier to be selected from a high speed data stream. high dynamic range decimation filters with a wide range of decimation rates allow both narrowband and wideband carriers to be extracted. the ram-based architecture allows easy reconfiguration for multi- mode applications. the decimating filters remove unwanted signals and noise from the channel of interest. when the channel of interest occupies less bandwidth than the input signal, this rejection of out-of- band noise is called ?rocessing gain.?by using large decimation factors, this ?rocessing gain?can improve the snr of the adc by 36 db or more. in addition, the programmable ram coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, cost- effective filter. the input port accepts a 16-bit mantissa, a 3-bit exponent, and an a/b select pin. these allow direct interfacing with the ad6600, ad6640, ad6644, ad9042 and most other high- speed adcs. three input modes are provided: single channel real, single channel complex, and diversity channel real. when paired with an interleaved sampler such as the ad6600, the ad6620 can process two data streams in the diversity channel real input mode. each channel is processed with coher- ent fr equency translation and output sample clocks. in addition, external synchronization pins are provided to facilitate coherent frequency translation and output sample clocks among several ad6620s. these features can ease the design of systems with diversity antennas or antenna arrays. units are packaged in an 80-lead pqfp (plastic quad flatpack) and specified to operate over the industrial temperature range (?0 c to +85 c). sharc is a registered trademark of analog devices, inc.
ad6620 C2C rev. a i-ram 256 18 c-ram 256 20 q-ram 256 18 m rcf rcf m cics cic5 scaling interleave de- interleave multi- plexer m cics cic2 scaling multi- plexer exp scaling frequency translator 3 18 18 i q 16 input data 3 exp[2:0] 16 in[15:0] complex nco f samp5 explnv, expoff timing sync i/o clk a/b reset sync rcf sync cic sync nco phase offset f samp2 f samp multiplexer scaling, s out serial parallel 16 23 23 dv out i/q out a/b out parallel outputs and serial i/o 16 out[15:0] sclk sdi sdo sdfs sdfe sbm wl[1:0] ad sdiv[3:0] rcf coefficients number of taps decimate factor address offset cic2, cic5 decimate factors scale factors nco frequency phase offset dither sync mask input mode real, dual, complex fixed or with exponent sync m/s output scale factor jtag trst tck tms tdi tdo microprocessor interface ds d[7:0] a[2:0] r/w dtack cs mode par/ser control registers microport and serial access ( w/r ) (rdy) ( r/d ) output figure 1. block diagram table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . 11 explanation of test levels . . . . . . . . . . . . . . . . 11 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin function descriptions . . . . . . . . . . . . . . . . . 12 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . 13 input data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output data port . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 frequency translator . . . . . . . . . . . . . . . . . . . . . 19 second order cascaded integrator comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 fifth order cascaded integrator comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ram coefficient filter . . . . . . . . . . . . . . . . . . . . . 25 control registers and on-chip ram . . . . . . . 27 programming the ad6620 . . . . . . . . . . . . . . . . . . . 30 access protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 microport control . . . . . . . . . . . . . . . . . . . . . . . . 32 serial port control . . . . . . . . . . . . . . . . . . . . . . . . 35 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . 37 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 44 architecture as shown in figure 1, the ad6620 has four main signal pro- cessing stages: a frequency translator, two cascaded integrator comb fir filters (cic2, cic5), and a ram coefficient fir filter (rcf). multiple modes are supported for clocking data into and out of the chip. programming and control is accom- plished via serial and microprocessor interfaces. input data to the chip may be real or complex. if the input data is real, it may be clocked in as a single channel or interleaved with a second channel. the two-channel input mode, called diversity channel real, is typically used in diversity receiver applications. input data is clocked in 16-bit parallel words, in[15:0]. this word may be combined with exponent input bits exp[2:0] when the ad6620 is being driven by floating-point or gain-ranging analog-to-digital converters such as the ad6600. frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (nco). real data entering this stage is separated into in-phase (i) and quadrature (q) components. this stage translates the input signal from a digital intermediate frequency (if) to baseband. phase and amplitude dither may be enabled on-chip to improve spurious performance of the nco. a phase offset word is available to create a known phase relationship between multiple ad6620s. following frequency translation is a fixed coefficient, high speed decimating filter that reduces the sample rate by a program- mable ratio between 2 and 16. this is a second order, cascaded integra tor comb fir filter shown as c ic2 in figure 1. (note: decimation of 1 in cic2 requires 2 or greater clock into ad6620). the data rate into this stage equals the input data rate, f samp . the data rate out of cic2, f samp2 , is determined by the decimation factor, m cic2 .
ad6620 C3C rev. a following cic2 is the second fixed-coefficient decimating filter. this filter, cic5, further reduces the sample rate by a program- mable ratio from 1 to 32. the data rate out of cic5, f samp5 , is determined by the decimation factors of m cic5 and m cic2 . each cic stage is a fir filter whose response is defined by the decimation rate. the purpose of these filters is to re duce the data rate of the incoming signal so that the final filter stage, a fir ram coef ficient sum-of-products filter (rcf), can calculate more taps per output. as shown in figure 1, on-chip multiplex- ers allow both cic filters to be bypassed if a multirate clock is used. the fourth stage is a sum-of-products fir filter with program- mable 20-bit coefficients, and decimation rates programmable from 1 to 32. the ram coefficient fir filter (rcf in figure 1) can handle a maximum of 256 taps. the overall filter response for the ad6620 is the composite of all three cascaded decimating filters: cic2, cic5, and rcf. each success ive filter stage is capable of narrower transi tion band- widths but requires a greater number of clk cycles to calculate the output. more decimation in the first filter stage will minimize overall power consumption. data comes out via a parallel port or a serial interface. figure 2 illustrates the basic function of the ad6620: to select and filter a single channel from a wide input spectrum. the freque ncy translator ?unes?the desired carrier to baseband. cic2 and cic5 have fixed order responses; the rcf filter provides the sharp transitions. more detail is provided in later sections of the data sheet. f s /2 3f s /8 5f s /16 f s /4 3f s /16 f s /8 f s /16 dc f s /16 f s /8 3f s /16 f s /4 5f s /16 f s /2 3f s /8 signal of interest signal of interest "image" wideband input spectrum ( f samp/ 2 to f samp/ 2) d' c' b' a' a c b d figure 2a. wideband input spectrum (e.g., 30 mhz from high-speed adc) f s /2 3f s /8 5f s /16 f s /4 3f s /16 f s /8 f s /16 dc f s /16 f s /8 3f s /16 f s /4 5f s /16 f s /2 3f s /8 after frequency translation nco "tunes" signal to baseband a b c d d' c' b' a' figure 2b. frequency translation (e.g., single 1 mhz channel tuned to baseband) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 cic2, cic5, and rcf dbc frequency figure 2c. baseband signal is decimated and filtered by cic2, cic5, rcf
C4C rev. a ad6620?pecifications recommended operating conditions test AD6620AS parameter level min typ max unit vdd i 3.0 3.3 3.6 v t ambient iv ?0 +25 +85 c electrical characteristics test AD6620AS parameter (conditions) temp level min typ max unit logic inputs 1, 2, 3, 4, 5, 6, 7 (not 5 v tolerant) logic compatibility full 3.3 v cmos logic ??voltage full i 2.0 vdd + 0.3 v logic ??voltage full i ?.3 0.8 v logic ??current full i 1 10 a logic ??current full i 1 10 a input capacitance 25 cv 4 pf logic outputs 2, 4, 7, 8, 9, 10, 11 logic compatibility full 3.3 v cmos/ttl logic ??voltage (i oh = 0.5 ma) full i 2.4 vdd ?0.2 v logic ??voltage (i ol = 1.0 ma) full i 0.2 0.4 v idd supply current clk = 20 mhz 12 full v 52 ma clk = 65 mhz 13 full i 167 227 ma reset mode 14 full i 1 ma power dissipation clk = 20 mhz 12 full v 170 mw clk = 65 mhz 13 full i 550 750 mw reset mode 14 full i 3.3 mw notes 1 input-only pins: clk, reset , in[15:0], exp[2:0], a/b, par/sel. 2 bidirectional pins: sync_nco, sync_cic, sync_rcf. 3 microinterface input pins: ds ( rd ), r/w ( wr ), cs . 4 microinterface bidirectional pins: a[2:0], d[7:0]. 5 jtag input pins: trst , tck, tms, tdi. 6 serial mode input pins: sdi, sbm, wl[1:0], ad, sdiv[3:0]. 7 serial mode bidirectional pins: sclk, sdfs. 8 output pins: out[15:0], dv out , a/b out , i/q out . 9 microinterface output pins: dtack (rdy). 10 jtag output pins: tdo. 11 serial mode output pins: sdo, sdfe. 12 conditions for idd @ 20 mhz. m cic2 = 2, m cic5 = 2, m rcf = 1, 4 rcf taps of alternating positive and negative full scale. 13 conditions for idd @ 65 mhz. m cic2 = 2, m cic5 = 2, m rcf = 1, 4 rcf taps of alternating positive and negative full scale. 14 conditions for idd in reset ( reset = 0). specifications subject to change without notice.
C5C rev. a ad6620 timing characteristics (c load = 40 pf all outputs) test AD6620AS parameter (conditions) temp level min typ max unit clk timing requirements: t clk clk period full i 14.93 1 ns t clk clk period full i 15.4 ns t clkl clk width low full iv 7.0 0.5 t clk ns t clkh clk width high full iv 7.0 0.5 t clk ns reset timing requirements: t resl reset width low full i 30.0 ns input data timing requirements: t si input 2 to clk setup time full iv ?.0 ns t hi input 2 to clk hold time full iv 6.5 ns parallel output switching characteristics: t dpr clk to out[15:0] rise delay full iv 8.0 19.5 ns t dpf clk to out[15:0] fall delay full iv 7.5 19.5 ns t dpr clk to dv out rise delay full iv 6.5 19.0 ns t dpf clk to dv out fall delay full iv 5.5 11.5 ns t dpr clk to iq out rise delay full iv 7.0 19.5 ns t dpf clk to iq out fall delay full iv 6.0 13.5 ns t dpr clk to ab out rise delay full iv 7.0 19.5 ns t dpf clk to ab out fall delay full iv 5.5 13.5 ns sync timing requirements: t sy sync 3 to clk setup time full iv ?.0 ns t hy sync 3 to clk hold time full iv 6.5 ns sync switching characteristics: t dy clk to sync 4 delay time full v 7.0 23.5 ns serial input timing: t ssi sdi to sclk t setup time full iv 1.0 ns t hsi sdi to sclk t hold time full iv 2.0 ns t hsrf sdfs to sclk u hold time full iv 4.0 ns t ssf sdfs to sclk t setup time 5 full iv 1.0 ns t hsf sdfs to sclk t hold time 5 full iv 2.0 ns serial frame output timing: t dse sclk u to sdfe delay time full iv 3.5 11.0 ns t sdfeh sdfe width high full v t sclk ns t dso sclk u to sdo delay time full iv 4.5 11.0 ns sclk switching characteristics, sbm = ? : t sclk sclk period 4 full i 2 t clk ns t sclkl sclk width low full v 0.5 t sclk ns t sclkh sclk width high full v 0.5 t sclk ns t sclkd clk to sclk delay time full v 6.5 13.0 ns s erial frame timing , sbm = ? : t dsf sclk u to sdfs delay time full iv 1.0 4.0 ns t sdfsh sdfs width high full v t sclk ns sclk timing requirements, sbm = ? : t sclk sclk period full i 15.4 ns t sclkl sclk width low full iv 0.4 t sclk 0.5 t sclk ns t sclkh sclk width high full iv 0.4 t sclk 0.5 t sclk ns notes 1 this specification valid for vdd >= 3.3 v. t clkl and t clkh still apply. 2 specification pertains to: in[15:0], exp[2:0], a/b. 3 specification pertains to: sync_nco, sync_cic, sync_rcf. 4 sclk period will be 2 t clk when ad6620 is serial bus master (sbm = 1) depending on the sdiv word. 5 sdfs setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad. specifications subject to change without notice.
ad6620 C6C rev. a timing characteristics (c load = 40 pf all outputs) test AD6620AS parameter (conditions) temp level min typ max unit microprocessor port, mode = 0 mode0 input timing requirements: t sc control 1 to clk setup time full iv 3.0 ns t hc control 1 to clk hold time full iv 5.0 ns t ha address 2 to clk hold time full iv 3.0 ns t zr cs to data enabled time full iv 5.0 ns t zd cs to data disabled time full iv 5.0 ns t sam cs to address/data setup time full iv 0.0 ns mode0 read switching characteristics: t dd clk to data valid time full i 10.0 15.0 30.0 ns t rdy rd to rdy time full iv 4.0 19.5 ns mode0 write timing requirements: t sc control 1 to clk setup time full iv 3.0 ns t hc control 1 to clk hold time full iv 5.0 ns t hm micro data 3 to clk hold time full iv 3.0 ns t ha address 2 to clk hold time full iv 3.0 ns t sam address/data setup time to cs full iv 0.0 ns mode0 write switching characteristics: t rdy rd to rdy time full iv 4.0 19.5 ns microprocessor port, mode = 1 mode1 input timing requirements: t sc control 1 to clk setup time full iv 3.0 ns t hc control 1 to clk hold time full iv 5.0 ns t ha address 2 to clk hold time full iv 3.0 ns t zr cs to data enabled time full iv 5.0 ns t zd cs to data disabled time full iv 5.0 ns t sam address/data setup time to cs full iv 0.0 ns mode1 read switching characteristics: t dd clk to data valid time full i 10.0 30.0 ns t dtack clk to dtack time full v 5.5 15.5 ns mode1 write timing requirements: t sc control 1 to clk setup time full iv 0.0 ns t hc control 1 to clk hold time full iv 5.0 ns t hm micro data 3 to clk hold time full iv 6.5 ns t ha address 2 to clk hold time full iv 3.0 ns t sam address/data setup time to cs full iv 0.0 ns mode1 write switching characteristic: t dtack clk to dtack time full v 5.5 15.5 ns notes 1 specification pertains to: r/w ( wr ), ds ( rd ), cs . 2 specification pertains to: a[2:0]. 3 specification pertains to: d[7:0]. specifications subject to change without notice.
ad6620 C7C rev. a timing diagrams clk, inputs, parallel outputs reset with par/ser = ??establishes parallel outputs active. t clkh t clkl t clk clk figure 3. clk timing requirements clk in[15:0] exp[2:0] a/b t si t hi data figure 4. input data timing requirements clk out[15:0] valid output data dv out i/q out t dpr t dpf i q i q i a q a i b q b t dpf figure 5. parallel output switching characteristics sync pulses: slave or master t sy t hy clk sync nco sync cic sync rcf note: in the slave mode with single channel operation, the width of the sync_nco should be one sample clock cycle. in dual channel mode, the pulsewidth should be two sample clock cycles. if a pulse longer than specified is used, the nco will be inhibited and not increment properly. figure 6. sync slave timing requirements clk t chp t cpl t cs t ch in[15:0] e[2:0] a/b n+1 n t clk figure 7. sync master delay t resl reset /t rlcr/lc
ad6620 C8C rev. a serial port: bus master reset with par/ser = ??establishes serial port active. sbm = ??puts ad6620 in serial bus master mode sclk is output; sdfs is output. t sclkd t sclkl t sclkh clk sclk t sclk figure 9. sclk switching characteristics t ssi t hsi data sdi sclk figure 10. serial input data timing requirements sclk t dsf t dse t sdfeh t sdfsh sdfs sdfe figure 11. serial frame switching characteristics t dso i 15 i 14 i 13 sclk sdo figure 12. serial output data switching characteristics serial port: cascade mode reset with par/ser = ??establishes serial port active. sbm = ??puts ad6620 in serial port cascade mode, sclk is input; sdfs is input. t sclk t sclkh t sclkl sclk figure 13. sclk timing requirements t ssi t hsi sclk sdi data figure 14. serial input data timing requirements t hsrf i 15 i 14 sclk sdo t hsf q 1 q 0 sdfs t ssf figure 15. sdo/sdfs timing requirements t dso i 15 i 14 sclk sdo t dse t sdfeh q 1 q 0 sdfe figure 16. sdo, sdfe switching characteristics
ad6620 C9C rev. a microport mode0, read timing is synchronous to clk; mode = 0. t dd data valid t hc t sc t hc t zd t ha t rdy t rdy address valid t sam t zr n n+1 n+2 n+3 n+4 n clk 1 wr 2 rd 2 cs 3 d[7:0] rdy 1 a[2:0] notes: 1 rdy is driven low asynchronously by rd and cs going low and returns high on the rising edge of clk "n+3" for internal access (a[2:0] = 000), clk "n+2" otherwise. 2 the signal, wr , may remain high and rd may remain low to continue read mode. 3 cs must return to high state and be sampled by clk (n+4 shown) to complete read. figure 17. mode0 read timing requirements and switching characteristics microport mode0, write timing is synchronous to clk; mode = 0. data valid t hc t sc t hc t sc t hm address valid n n+1 n+2 n+3 n* clk 1 wr 2 rd 2 cs 3 d[7:0] rdy a[2:0] notes: 1 rdy is driven low asynchronously by wr and cs going low and returns high on the rising edge of clk "n+2". 2 these signals (r/w and ds ) may remain in low state to continue writing data. 3 cs must return to high state and be sampled by clk (n+3 shown) to complete write. * the next write may be initiated on clk, n*. t ha t rdy t rdy t sam t sam figure 18. mode0 write timing requirements and switching characteristics
ad6620 C10C rev. a microport mode1, read timing is synchronous to clk; mode = 1. data valid t sc address valid n n+1 n+2 n+3 clk 1 r/w 2 ds 2 cs 3 d[7:0] dtack a[2:0] t sam n+4 n t hc t dd t hc t zd t ha t dtack t dtack notes: 1 dtack is driven low on the rising edge of clk "n+3" for internal access (a[2:0] = 000), clk "n=2" otherwise. 2 the signal, r/w may remain high and ds may remain low to continue read mode. 3 cs must return to high state and be sampled by clk (n+4 shown) to complete access and force dtack high. t sc t zr figure 19. mode1 read timing requirements and switching characteristics microport mode1, write timing is synchronous to clk; mode = 1. t sc n n+1 n+2 n+3 t sam n* t dtack t sc clk 1 r/w 2 ds 2 cs 3 d[7:0] dtack a[2:0] t hc t hc t dtack t sam t hm t ha notes: 1 on rising edge of "n+3" clk, dtack is driven low. 2 these signals (r/w and ds ) may remain in low state to continue writing data. 3 cs must return to high state and be sampled by clk (n+3 shown) to complete write and force dtack high. * the next write may be initiated on clk, n*. data valid address valid figure 20. mode1 write timing requirements and switching characteristics
ad6620 C11C rev. a absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +4.5 v input voltage . . . ?.3 v to vdd + 0.3 v (not 5 v tolerant) output voltage swing . . . . . . . . . . . . ?.3 v to vdd + 0.3 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . 130 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . 280 c * stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 80-lead plastic quad flatpack: ja = 44 c/w jc = 11 c/w explanation of test levels i. 100% production tested. ii. 100% production tested at 25 c, and sampled tested at specified temperatures. iii. sample tested only. iv. parameter guaranteed by design and analysis. v. parameter is typical value only. vi. 100% production tested at 25 c, and sampled tested at temperature extremes. ordering guide package model temperature range package description option AD6620AS ?0 c to +85 c (ambient) 80-lead pqfp (plastic quad flatpack) s-80a ad6620s/pcb evaluation board with AD6620AS and software caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad6620 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad6620 C12C rev. a name type description vdd p 3.3 v supply vss g ground clk i input clock reset i active low reset pin in[15:0] i input data (mantissa) exp[2:0] i input data (exponent) a/b i channel (a/b) select sync_nco i/o sync signal for nco sync_cic i/o sync signal for cic stages sync_rcf i/o sync signal for rcf mode i sets microport mode: mode 1, (mode = 1), mode 0, (mode = 0) a[2:0] i mi croprocessor interface ad dress d[7.0] i/o/t microprocessor interface data ds or rd i mode 1: data strobe line, mode 0: read signal r/w or wr i read/write line (write signal) cs i chip select, enables the chip for p access dtack or rdy o acknowledgment of a com pleted transaction (signals when p port is ready for an access) par/ser i parallel/serial control select (par = 1, ser = 0) dv out o data valid pin for the parallel output data a/b out o signals to which channel the output belongs to (a = 1, b = 0) i/q out o signals whether i or q data is present (i = 1, q = 0) trst i test reset pin tck i test clock input tms i test mode select input tdi i test data input tdo i test data output pin types: i = input, o = output, p = power supply, g = ground, t = three-state. shared pins parallel outputs (par/ser = 1 at reset) serial port (par/ser = 0 at reset) name type description name type description out15 o parallel output data sclk i/o serial clock input (sbm =0) serial clock output (sbm = 1) out14 o parallel output data sdi i serial data input out13 o parallel output data sdo o/t serial data output out12 o parallel output data sdfs i/o serial data frame sync input (sbm = 0) serial data frame sync output (sbm = 1) out11 o parallel output data sdfe o serial data frame end out10 o parallel output data sbm i serial bus master (master = 1, cascade = 0) out9 o parallel output data wl1 i serial port word length, bit 1 out8 o parallel output data wl0 i serial port word length, bit 0 out7 o parallel output data ad i append data out[6:4] o parallel output data nc nc unused, do not connect out3 o parallel output data sdiv3 i sclk divide value, bit 3 out2 o parallel output data sdiv2 i sclk divide value, bit 2 out1 o parallel output data sdiv1 i sclk divide value, bit 1 out0 o parallel output data (lsb) sdiv0 i sclk divide value, bit 0 pin types: i = input, o = output, p = power supply, g = ground, t = three-state. pin function descriptions
ad6620 C13C rev. a pin configurations parallel output data 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) d7 (msb) out15 out14 vdd out13 out12 out11 vss out10 out9 out8 out7 vdd out6 out5 out4 d6 d5 d4 vss d3 d2 d1 vdd d0 ds dtack r/w vss mode a2 a1 out0 (lsb) a/b out i/q out vdd dv out par/ser reset trst tck tms tdo tdi vdd sync nco sync cic sync rcf vss exp2 in15 (msb) in14 vss in13 in12 in11 vdd in10 in9 in7 vss in6 in5 in4 in8 ad6620 vss out3 out2 out1 clk a/b in0 (lsb) vdd in3 in2 in1 a0 cs exp0 exp1 serial port 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) d7 sclk sdi vdd sdo sdfs sdfe vss sbm wl1 wl0 ad vdd nc nc nc d6 d5 d4 vss d3 d2 d1 vdd d0 ds dtack r/w vss mode a2 a1 sdiv0 a/b out i/q out vdd dv out par/ser reset trst tck tms tdo tdi vdd sync nco sync cic sync rcf vss exp2 in15 in14 vss in13 in12 in11 vdd in10 in9 in7 vss in6 in5 in4 in8 ad6620 vss sdiv3 sdiv2 sdiv1 clk a/b in0 vdd in3 in2 in1 a0 cs exp0 exp1 the highest numbered bit is the msb for all ports nc = no connect
ad6620 C14C rev. a cic2 decimation log 2 (m) 225 5 1 power mw 234 250 275 300 325 350 375 400 cic5 decimation rcf decimation tpc 1. typical power vs. decimation rates 0 132 120 108 96 84 72 60 48 36 24 12 0 f samp spur = 104db phase dither off tpc 2. typical nco spur without dither 0 132 120 108 96 84 72 60 48 36 24 12 0 f samp spur = 118db phase dither on tpc 3. typical nco spur with dither typical performance characteristics 0 1 140 120 100 80 60 40 20 0 rejection db composite frequency response mhz 23 tpc 4. high decimation gsm filter input sample rate 65 msps, decimation is 240, fir taps is 240. unshown spectrum is below that shown. decimation distribu- tion is 3, 10, 8, respectively. 0 2 140 120 100 80 60 40 20 0 rejection db composite frequency response mhz 48 6 tpc 5. high decimation amps filter input sample rate 58.32 msps, decimation is 300, fir taps is 128. unshown spectrum is below that shown. decimation dis tri- bution among cic2, cic5, and rcf is 10, 30 and 1, respectively.
ad6620 C15C rev. a input data port the input d ata port accepts a clock (clk), a 16-bit mantissa in[15:0], a 3-bit exponent exp[2:0], and channel select pin a/b. these pins allow direct interfacing to both standard fixed-point adcs such as the ad9225 and ad6640, as well as to gain- ranging adcs such as the ad6600. these inputs are not 5 v tolerant and the adc i/o should be set to 3.3 v. the input data port accepts data in one of three input modes: single channel real, diversity channel real, or single channel complex. the input mode is selected by programming the input mode control register located at internal address space 300h. single channel real mode is used when a single channel adc drives the input to the ad6620. diversity channel real mode is the two channel mode used primarily for diversity receiver appli- cations. single channel complex mode accepts complex data in conjunction with the a/b input which identifies in-phase and quadrature samples (primarily for cascaded 6620s). the input data port is sampled on the rising edge of clk at a maximum rate of 67 msps. the 16-bit mantissa, in[15:0] is interpreted as a twos complement integer . for most applications with adcs having fewer than 16 bits, the active bits should be msb justified and the unused lsbs should be tied low. the 3-bit exponent, exp[2:0] is interpreted as an unsigned integer. the exponent can be modified by the 3-bit exponent offset expoff (control register 0x305, bits (7?)) and an expo- nent invert expinv (control register 0x305, bit 4). expoff sets the offset of the input exponent, exp[2:0]. expinv determines the direction of this offset. equati ons below show how the exponent is handled. scaled input in expinv exp expoff _, mod( , ) = = + 20 8 scaled input in expinv exp expoff _, mod( ,) = = + 21 78 where: in is the value of in[15:0], exp is the value of exp[2:0], and expoff is the value of expoff. input scaling in gene ral there are two reasons for scaling digital data. the first is to avoid clipping or, in the case of the ad6620 regis- ter, wrap-around in subsequent stages. wrap-around is not a concern for the input data since the nco is designed to accept the largest possible input at the ad6620 data port. the second use of scaling is to preserve maximum dynamic range through the chip. as data flows from one stage to the next it is important to keep the math functions performed in the msbs. this will keep the desired signal as far above the noise floor as possible, thus maximizing signal-to-noise ratio. scaling with fixed-point adcs for fixed-point adcs, the ad6620 exponent inputs exp[2:0] are typically not used and should be tied low. the adc outputs are tied directly to the ad6620 inputs, msb-justified. the exponent offset (expoff) and exponent invert (expinv) should both be programmed to 0. thus the input equation, scaled input in expinv exp expoff _, mod( , ) = = + 20 8 where: in is the value of in[15:0], exp is the value of exp[0:2], and expoff is the value of expoff, simplifies to, scaled input in _ mod( , ) = 2 08 thus for fixed-point adcs, the exponents are typically static and no input scaling is used in the ad6620. in4 in3 in2 in1 in0 exp2 exp1 exp0 in15 d11 (msb) d0 (lsb) ad6640 ad6620 a/b +3.3v figure 21. typical interconnection of the ad6640 fixed point adc and the ad6620 scaling with floating-point adcs an example of the exponent control feature combines the ad6600 and the ad6620. the ad6600 is an 11-bit adc with three bits of gain ranging. in effect, the 11-bit adc provides the mantissa, and the three bits of relative signal strength indicator (rssi) are the exponent. only five of the eight available steps are used by the ad6600. see the ad6600 data sheet for additional details. for gain-ranging adcs such as the ad6600, scaled input in expinv exp expoff _, mod( ,) = = + 21 78 where: in is the value of in[15:0], exp is the value of exp[2:0], and expoff is the value of expoff. the rssi output of the ad6600 numerically grows with increas- ing s ignal strength of the analog input (rssi = 5 for a large signal, rssi = 0 for a small signal). with the exponent offset equal to zero and the exponent invert bit equal to zero, the ad6620 would consider the smallest signal at the parallel input (exp = 0) the largest and, as the signal and exp word increase, it shifts the data down internally (exp = 5, will shift the 11-bit data right by 5 bits internally before going into the cic2). the ad6620 regards the largest signal p ossible on the ad6600 as the smallest signal. thus the exponent invert bit is used to make the ad6620 exponent agree with the ad6600 rssi. w hen it is set high, it forces the ad6620 to shift the data up for growing exp instead of down. the exponent invert bit should always be set high for use with the ad6600. table i. ad6600 transfer function with ad6620 expinv = 1, and no expoff adc input ad6600 ad6620 signal level rssi[2.0] data reduction largest 101 (5) 4 (>> 2) 12 db 100 (4) 8 (>> 3) 18 db 011 (3) 16 (>> 4) 24 db 010 (2) 32 (>> 5) 30 db 001 (1) 64 (>> 6) 36 db smallest 000 (0) 128 (>> 7) 42 db (expinv = 1, expoff = 0)
ad6620 C16C rev. a the exponent offset is used to shift the data right. for example, table i shows that with no expoff shift, 12 db of range is lost when the adc input is at the largest level. this is undesired because it lowers the dynamic range and snr of the system by reducing the signal of interest relative to the quantization noise floor. to avoid this automatic attenuation of the full-scale adc sig- nal, the exponent offset is used to move the largest signal (rssi = 5) up to the point where there is no downshift. in other words, once the exponent invert bit has been set, the exponent offset should be adjusted so that mod(7 5 + expoff,8) = 0. this is the case when exponent offset is set to 6 since mod(8, 8) = 0. table ii illustrates the use of expinv and expoff when used with the ad6600 adc. table ii. ad6600 transfer function with ad6620 expinv = 1, and expoff = 6 adc input ad6600 ad6620 signal level rssi[2.0] data reduction largest 101 (5) 1 (>> 0) 0 db 100 (4) 2 (>> 1) 6 db 011 (3) 4 (>> 2) 12 db 010 (2) 8 (>> 3) 18 db 001 (1) 16 (>> 4) 24 db smallest 000 (0) 32 (>> 5) 30 db (expinv = 1, expoff = 6) this flexibility in handling the exponent allows the ad6620 to interface with other gain ranging adcs besides the ad6600. the exponent offset can be adjusted to allow up to seven rssi(exp) ranges to be used as opposed to the ad6600s five. it also allows the ad6620 to be tailored in a system that employs the a d6600, but does not utilize all of its signal range. for example, if only the first four rssi ranges are expected to occur then the exponent offset could be adjusted to five, which would then make rssi = 4 correspond to the 0 db point of the ad6620. in4 in3 in2 in1 in0 exp2 exp1 exp0 in15 d10 (msb) d0 (lsb) ad6600 ad6620 a/b rss12 rss11 rss10 a/b out figure 22. typical interconnection of the ad6600 gain- ranging adc and the ad6620 in a diversity application input timing the clk signal is used to sample the input port and clock the synchronous signal processing stages that follow. the clk signal can operate up to 67 mhz and have a duty cycle of 45% to 55%. in applications using high speed adcs, the adc sample clock is typically used to clock the ad6620. applications that require a faster signal processing clock than the adc sample clock, may employ fractional rate input timing as shown in the following sections. the input timing requirements vary according to the mode of operation. fractional rate input timing creates a longer don t care time for the input data so that slower adcs need only meet the setup-and-hold conditions for their data with respect to their own sample clock cycle, rather than the faster signal processing clock. the adc sample clock may be any integer fraction of clk up to and including 1, as long as the clock and data rate are less than or equal to 67 msps. single channel real mode in the single channel real mode the a/b input pin functions as an active high input enable. if the a/d sample clock is fast enough to perform the necessary filter functions, full rate input timing can be used and a/b should be tied high as shown in figure 23. n n+1 n+2 n+3 n+4 t si t hi clk in[15:0] exp[2:0] a/b figure 23. full rate in put timing, single channel real mode when a faster processing clock is used to achieve better filter performance, the a/d data must be synchronized with the faster ad6620 clk signal. this is achieved by having the adc clock rate an integer fraction of the ad6620 clock rate. ad6620 input data is sampled at the slower adc clock rate. in the single channel real mode this is achieved by dynamically controlling the a/b input and bringing it high before each rising clk edge that data is to be sampled on. a/b must be returned low before the next high speed clock pulse and the duty cycle of the a/b signal will therefore be equal to the data-to-clock ratio. n n+1 t si t hi clk in[15:0] exp[2:0] a/b figure 24. fractional rate input timing (4 clk), single channel real mode diversity channel real mode in the diversity channel real mode the a/b pin serves not only as an input enable but also to determine which channel is being sampled on a given clk edge. a high on the a/b pin marks channel a data and a low on a/b marks channel b data. the ad6620 only accepts the first sample after an a/b transition. all subsequent samples are disregarded until a/b changes again. when full rate input timing is employed in the diversity chan- nel real mode, a/b must toggle on every rising edge of clk for new data to be clocked into the ad6620.
ad6620 C17C rev. a t si t hi clk in[15:0] exp[2:0] a/b b n b n+1 a n+1 a n+2 b n+2 clk 2x a n if clk 2x is used to clock the ad6620, the first rising edge after the a/b transition will latch the data. figure 25. full rate input timing, diversity channel real mode if fractional rate input timing is necessary in the diversity chan- nel real mode, the a/b pin must toggle at half the rate of the a/d sample clock. the timing diagram below shows a 3 pro- cessing clock. in this situation there will be one adc encode pulse for every three ad6620 clk pulses and data must be taken on every third clk pulse. the clk edges that corre- spond to the latching of a and b channel data are shown in figure 26. a n t si t hi clk in[15:0] exp[2:0] a/b b n figure 26. fractional rate input timing (3 clk), diversity channel real mode single channel complex mode in the single channel complex input mode, a/b high identi- fies the in-phase samples and a/b low identifies quadrature samples. the quadrature samples are paired with the previous in-phase samples. the timing for this mode is the same as that of the diversity channel real mode. this mode is useful for accepting complex output data from another ad6620 or another source to increase filtering and or decimation rates. in the single channel complex mode the cic2 decimation must be set to two (m cic2 = 2). this is necessary in order to allow enough clk cycles to process the complex input data as described below. first clock cycle: (a/b high). i data loaded from the input port. the i data-path gets i cosine. the q data-path gets i sine. the first integrator of the cic2 adds these values to its previous sums. the rest of the cic2 is idle. second clock cycle: (a/b low). q data loaded from the input port. the i data-path gets q sine. the q data-path gets q cosine. the first integrator of the i path of the cic2 completes the sum (i cosine - q sine) and the first integrator of the q path of the cic2 completes the sum j(i sine + q cosine). the rest of the cic2 operates on these sums, which is the complete complex multiply. the data is then multiplexed through the rest of the chip as if it were single channel real data. simplified input data port schematic figure 27 details a simplified schematic for the input data port. the first thing to note is that in[15:0], exp[2:0] and a/b are all synchronously latched with clk. note also that upon soft reset, a seven pipeline delay (sample clock delay) exists in the data path. this delay is synchronous with clk, but is in fact seven valid sample data delays. for instance, in single channel clk logic "1" soft reset clr q q d enb q d in[15:0] exp[2:0] q d a/b clk register q d q d register clk multiplexer d s 1 s 2 c dual channel real single channel complex int in[15:0] int exp[2:0] int data strobe clr delay 7 enb d set q clr q figure 27. simplified input data port schematic for the ad6620
ad6620 C18C rev. a real mode with full rate timing the delay is seven clks. if instead the data rate is one-fourth clk, then 28 clks (i.e., seven sample data delays, gated via a/b) occur before valid data is passed to the nco stage. interfacing ad6620 inputs to 5 v logic gates none of the inputs to the ad6620 are tolerant of 5 v logic signals. when interfacing 5 v devices to this product, an interface gate such as the 74lcx2244 is recommended. if latching must be performed, 74lcx574 latches may be used. this gate runs from the 3.3 v supply and is tolerant of 5 v inputs. output data port parallel output data port the ad6620 provides a choice of two output ports: a 16-bit parallel port and a synchronous serial port. output operation using the serial port is discussed in the next section. the parallel port is limited to 16 bits. because pins are shared between the parallel and serial output ports, only one output mode can be used. the output mode must be set with a hard reset generated by at least a 30 ns low time on the reset pin. if the par/ser line is high (logic 1 ), then parallel output data is activated. the par/ser pin should remain static after the output mode has been set (i.e., par/ser should only change when reset is low). data out of the ad6620 is two s complement. a scale factor is associated with the output port, which allows the signal level to be adjusted. this scale factor is mapped to location 309h, bits 2 0 in the ad6620 internal address space. this scalar controls the weight of the 16-bit data going to the parallel port. the scale factor is discussed in the ram coeffi- cient filter (rcf) section. the parallel mode provides a 16-bit output port, which consti- tutes the i and q data for either one or both channels. this port can run at a maximum of 67 mhz (33.5 mhz i, 33.5 mhz q). this rate assumes that there is a minimum decimation of 2 in the first filter stage (cic2) or a 2 or greater clk is used. this decimation is required because for every input word there is both an i and a q output. when the data rate and clock rate are the same (full rate input timing), the minimum decimation of 2 must occur in cic2. refer to cic2 for more detail. dv out dv out is provided to signal that valid data is present. if this pin is high, there is a valid data word on the bus. dv out remains high for two high-speed clock cycles in single channel real and single channel complex mode and for four high-speed clock cycles in diversity channel real mode. after dv out returns low the q data will remain until the next data sample. i/q out when this pin is high the data word represents i data; when i/q out is low q data is present. this signal will also be low when dv out is low since the last word of every data phase is q data. a/b out if dv out is low, a/b out is always low. when a/b out is high, a channel data is available on the output. if dv out remains high while a/b out is low, then b channel data is on the output pins of the chip out[15:0]. clk out[15:0] valid data a data t dpr t dpf t dpf iq i a q a dv out i/q out a/b out figure 28. parallel output data timing (single-channel mode) t dpr t dpf t dpf t dpf iq iq i a q a i b q b valid data a data b data clk out[15:0] dv out i/q out a/b out figure 29. parallel output data timing (diversity channel mode) serial output data port the ad6620 provides a choice of two output ports: a 16-bit parallel port and a synchronous serial port. the advantage of using the serial port is that all 23 bits of available data can be output in the 24-bit or 32-bit mode. the serial output port shares some of the same pins used by the parallel output port. as a result, one or the other mode of output may be utilized, but not both. the output mode must be set with a hard reset generated by at least a 30 ns low time on the reset pin. if the par/ser line is low (logic 0 ) upon reset, then serial output data is activated. the par/ser pin should remain static after the output mode has been set (i.e., par /ser should only change when reset is low). note that the ad6620 cannot be booted through the serial port. the microport must be used to initialize the device, then serial operation is supported. figure 30 shows the typical interconnections between an ad6620 in serial master mode and a dsp. refer to the serial control port section for a detailed description of pin functions and pro- cedures for writing and reading with relation to the serial port. note the 10 k ? resistors connected to sdi and sdo. these prevent the lines from toggling when the ad6620 or dsp three-states these pins.
ad6620 C19C rev. a sclk ad6620 dsp +3.3v sbm sclk sdi dt sdo dr sdfs rfs sdfe 10k 10k sdiv 2 4 ad wl figure 30. typical serial data output interface to dsp (serial master mode, sbm = 1) figure 31 shows two ad6620s illustrating the cascade capability for the chip. the first is connected as a serial master and the second is configured in serial cascade mode. the sdfe signal of the master is connected to the sdfs of the slave. this allows the master ad6620 data to be obtained first by the dsp, fol- lowed by the cascaded ad6620 data. sclk ad6620 dsp +3.3v sbm sclk sdi dt sdo dr sdfs rfs sdfe 10k sdiv 2 4 ad wl 10k sclk ad6620 cascade sbm sdi sdo sdfs sdfe sdiv 2 4 ad wl figure 31. typical serial data output interface to dsp (serial cascade mode, sbm = 0) the ad6620 also supports a serial slave mode, where the serial clock and interface is provided by a dsp or asic that is set to operate in the master mode. note that the ad6620 cannot be booted through the serial port. the microport must be used to initialize the device, then serial operation is supported. in the serial slave mode, dv out is valid and indicates the pres- ence of a new word in the output buffers of the shift register. this pin may thus be used by the dsp to generate an interrupt to service the serial port. the dsp then generates an sfds pulse to drive the ad6620. the first serial clock rising edge after sdfs makes the first bit available at sdo. the falling edge of serial clock can be used to sample the data. the total number of bits are then read from the ad6620 (determined by the serial port word length). if the dsp has the ability to count bits, the dsp will know when the complete frame is read. if not, the dsp can monitor the sdfe pin to determine that the com- plete frame is read. the serial clock provided by the dsp can be asynchronous with the ad6620 clock and input data. sclk ad6620 dsp sbm sclk sdi dt sdo dr sdfs rfs sdfe 10k 10k sdiv 2 4 ad wl dv out irq figure 32. typical serial data output interface to dsp (serial slave mode, sbm = 0) in either the serial master or slave mode, there are two con- straints that must be observed. the first is that the clock must be fast enough to read the serial frame prior to the next frame becoming available. since the ad6620 output is synchronous with its input sample rate, the output update rate can be deter- mined by the user-programmed decimation rate. the timing diagram in figure 33 details how serial slave mode is imple- mented. the second constraint is that the time between serial frames may be either zero sclk periods (the end of one frame adjoins the beginning of the next) or two or more sclk peri- ods. one sclk period between frames is not allowed. t dso dv out sclk sdfs sdo dsp uses falling edge of dv out to generate sdfs first data is available the first rising sclk after sdfs goes high i msb i msb 1 dv out pulsewidth is 2 clkin single channel and 4 clkin dual channel figure 33. timing for serial slave mode (sbm = 0) frequency translator the first signal p rocessing stage is a frequency translator con- sisting of two multipliers and a 32-bit complex numerically controlled oscillator (nco). the nco serves as a quadrature local oscillator capable of producing any analytic frequency between f samp /2 and +f samp /2 with a resolution of f samp /2 32 . in the single channel real input mode, f samp is equal to f clk multi- plied by the fraction of clk cycles that a/b is high. in the diversity channel real and single channel complex input
ad6620 C20C rev. a modes, f samp is equal to f clk multiplied by the fraction of clk cycles on which a/b has been toggled. the nco worst case discrete spur is better than 100 dbc for all output frequencies. the control word, nco_freq is interpreted as a 32-bit unsigned integer. to translate a channel centered at f ch to dc, calculate nco_freq using the equation below. the mod function is used here to allow for super nyquist sampling where the if carrier (fch) is larger than the sample rate (fsamp). the mod removes the integer portion of the number and forces it into the 32-bit nco frequency register. if the fraction rem aining is larger than 0.5, the nco will be tuning above the nyquist rate. the corresponding signal is then aliased back into the first nyquist zone as a negative frequency. nco freq f f ch samp _, = ? ? ? ? ? ? 21 32 mod in both single and diversity channel real input modes, the out- put of the translation stage is the complex product of the real input samples and the complex samples from the nco. it is necessary for the subsequent decimating filters to reject the unwanted image of the channel of interest, as well as any unwanted neighboring signals (and their images) not rejected by previ- ous analog filters. in the diversity channel real input mode, the same nco output words are used for both channel a and b streams, resulting in identical phase shifts. in single channel complex mode both i and q inputs are multiplied by the quadrature outputs of the nco. the i and q products of the multiply are then processed in the ad6620 filter stages. in single channel real or dual channel real operation, the frequency translation and filtering processes provide a gain of 6 db. this can be visualized since the input data is usually a real sampled signal consisting of both positive and negative frequency compo- nents (figure 2a). after being mixed with the complex nco, the normal filtering of the ad6620 will remove one component or the other resulting in an analytic signal (figure 2b). this filtering thus removes one-half or 6 db of the signal keeping consistent with the mathematics involved. if however, the filter- ing of the device allows both the positive and negative frequency components to pass (i.e., the original signal is near dc), the gain of the frequency translation is 0 db. finally, if the nco is bypassed, the gain of the frequency translation block is 12 db. phase dither the ad6620 provides a phase dither option for improving the spurious performance of the nco. this is controlled via the nco control register at address 301 hex. when phase dither is enabled by setting bit 1 of this register high, spurs due to phase truncation in the nco are randomized. the energy from these spurs is spread into the noise floor and spurious free dynamic range is increased at the expense of very slight decreases in the snr. phase dither should be experimented w ith for each desired nco frequency and if it is seen to reduce spurs, it should be considered. the choice of whether phase dither is used in a system will ultimately be decided by the system goals. if lower spurs are desired at the expense of a slightly raised noise floor, it should be employed. if a low noise floor is desired and the higher spurs can be tolerated or filtered by subsequent stages, then phase dither is not needed. amplitude dither the second dither option is amplitude dither or complex dither. amplitude dither is enabled by setting bit 2 of the nco control register at address 0x301 high. amplitude dither improves performance by randomizing the amplitude quantiza- tion errors within the angular to cartesian conversion of the nco. this dither will be particularly useful when the nco frequency is close to an integer submultiple of the input data rate. however, this option may reduce spurs at the expense of a slightly raised noise floor. amplitude dither and phase dither can be used together, separately or not at all. phase offset the phase offset register adds an offset to the phase accumula- tor of the nco. this is a 16-bit register and is interpreted as a 16-bit unsigned integer. a 0 in this register corresponds to a 0 radian offset and an ffff hex corresponds to an offset of 2 (1 1/(2^16)) radians. this register can be used to allow mul- tiple ad6620s whose ncos are synchronized to produce sine waves with a known and steady phase difference. nco synchronization in order to achieve phase coherence between several ad6620s, a sync_nco pin is provided. when the internal register bit, sync_m/s (bit 3 of internal register 0x300), is set high, sync_nco provides a synchronization pulse on the rising edge of clk. when the sync_m/s bit is low, sync_nco accepts an external synchronization signal sampled on the rising edge of clk. when the ad6620 is a slave, the sync_nco signal need not be a short pulse. it may be taken high and held for more than a clk cycle in which case the nco will be held inactive until this pin is again lowered. if the device is run as a sync slave in single channel mode, the sync_nco pin must be held low for one sample period, usually one clock cycle. if the device is run in diversity channel real mode, the sync_nco must be high for two sample periods (clock cycles). in a system with an array of ad6620s it is not necessary to use one as a master. it may be desirable to generate a synchronization signal elsewhere in the system and use that to control the ad6620. an example of this may be in systems that receive packets of data. in this case, the nco may be resynchronized prior to the begin- ning of the packet, thus giving a consistent phase relationship on each burst. this allows for ease of use in a large system where many ad6620s need be synchronized accurately across a large backplane or installation. t dy clk sync nco sync cic sync rcf note: in the slave mode with single channel operation, the width of the sync_nco should be one sample clock cycle. in dual channel mode, the pulsewidth should be two sample clock cycles. if a pulse longer than specified is used, the nco will be inhibited and not increment properly. figure 34. sync_nco pin
ad6620 C21C rev. a the frequency of the sync_nco pulses, and therefore the accuracy of the synchronization, is determined by the value of the nco sync control register at address 302 hex. the value in this register is the sync_mask and is interpreted as a 32-bit unsigned integer. this value controls the window around the zero crossing of the nco output sine wave in which the nco will output a sync_nco pulse as a master. as a slave, the value in this register will determine the number of msbs of the output sine wave that are synchronized with the master. the master and all slaves should use the same sync_mask word. this value should almost always be written as all 1s (ffffffff hex). effects of a/b input on the nco if the ad6620 is run in single channel real mode using frac- tional rate input timing, the a/b input is used to enable the nco advancement. if the a/b line is held high longer than one clock period, the nco will advance for each rising edge of the clk while a/b is high. this is not normally the desired result and thus a/b must be taken low after the first clk period to prevent anomalous nco results. see additional details under fractional rate timing. phase continuous tuning with the ad6620 for synchronization purposes, the ad6620 nco phase is reset each time the nco frequency register is either written to or read from. this is accomplished by forcing an nco sync to occur. normally, phase-continuous tuning is required on the transmit path to control spectral leakage. on the receive path this in not usually a constraint. however, if phase-continuous tuning is required with the ad6620, it can be accomplished by configuring the ad6620 as a sync slave. in this manner, no internal nco sync is generated when the nco frequency regis- ter is written to. if multiple ad6620s are synchronized together, a common external sync pulse can be used to lock each of the receivers together at the appropriate point in time. it is also possible to reconfigure the ad6620 after the nco frequency register has been written so that the chip is once again a sync master. the next time the nco phase cycles through 0 degrees, the nco sync is exerted and the chip is again synchronized. 2nd order cascaded integrator comb filter the cic2 filter is a fixed-coefficient, decimating filter. it is constructed as a second order cic filter whose characteristics are defined only by the decimation rate chosen. this filter can process signals at the full rate of the input port (67 mhz) in all input modes. the output rate of this stage is given by the equa- tion below. f f m samp samp cic 2 2 = the decimation ratio, mcic2, is an unsigned integer that may be between 1 and 16. this stage may be bypassed under certain conditions by setting, m cic2 equal to 1. for this to happen the processing clock rate, f clk must be two or more times the input data rate, f samp . this is because the i and q data is processed in parallel within the cic2 filter, and the i and q output data is then multiplexed through the same data pipe before it enters the cic5 filter. the frequency response of the cic2 filter is given by the follow- ing equations. hz z z s m cic cic () = ? ? ? ? ? ? 1 2 1 1 2 2 1 2 hf mf f f f s cic samp samp cic () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 2 2 2 the scale factor, s cic2 is a programmable unsigned integer between 0 and 6. this serves as an attenuator that can reduce the gain of the cic2 in 6 db increments. for the best dynamic range, s cic2 should be set to the smallest value possible (i.e., lowest attenuation) without creating an overflow condition. this can be s afely accomplished using the equation below, where input_level is the largest fraction of full scale possible at the input to this ad6620 (normally 1). the cic2 scale factor is not ignored when the cic2 is bypassed. register register 1 masked count = 0? sync mask sync_nco pin 1 1 32 32 32 32 1 0 32 32 32 32 32 nco freq amplitude dither cos sin phase dither phase offset phase accumulator x4 register figure 35. nco block diagram
ad6620 C22C rev. a s ceil m input level ol input level cic cic cic s cic 222 2 2 1 2 2 = ? ? ? ? = log ( _ ) _ the equations for calculating cic2 output level is correct when stage is not bypassed (normal operation). however, when by- passed, the following equations should be used instead. ol cic 2 = input level the gain and pass band droop of the cic2 should be calculated by the equations above, as well as the filter transfer equations that follow. if these are unacceptable, they can be compensated for in subsequent stages. cic2 rejection the table below illustrates the amount of bandwidth in percent of the data rate into the cic2 stage. the data in this table may be scaled to any allowable sample rate up to 67 mhz in single channel mode or 33.5 mhz in diversity channel mode. the table can be used as a tool to decide how to distribute the deci- mation between cic2, cic5 and the rcf. the data in this table may be scaled to any allowable sample rate up to 67 mhz in single channel mode or 33.5 mhz in diversity channel mode. table iii. ssb cic2 alias rejection table (f samp = 1) bandwidth shown in percentage of f samp m cic2 ?0 db ?0 db ?0 db ?0 db ?0 db ?00 db 2 1.79 1.007 0.566 0.318 0.179 0.101 3 1.508 0.858 0.486 0.274 0.155 0.087 4 1.217 0.696 0.395 0.223 0.126 0.071 5 1.006 0.577 0.328 0.186 0.105 0.059 6 0.853 0.49 0.279 0.158 0.089 0.05 7 0.739 0.425 0.242 0.137 0.077 0.044 8 0.651 0.374 0.213 0.121 0.068 0.038 9 0.581 0.334 0.19 0.108 0.061 0.034 10 0.525 0.302 0.172 0.097 0.055 0.031 11 0.478 0.275 0.157 0.089 0.05 0.028 12 0.439 0.253 0.144 0.082 0.046 0.026 13 0.406 0.234 0.133 0.075 0.043 0.024 14 0.378 0.217 0.124 0.07 0.04 0.022 15 0.353 0.203 0.116 0.066 0.037 0.021 16 0.331 0.19 0.109 0.061 0.035 0.02 example calculations goal: implement a filter with an input sample rate of 10 mhz requiring 100 db of alias rejection for a 7 khz pass band. solution: first determine the percentage of the sample rate that is represented by the pass band. bw khz mhz fraction = = 100 7 10 007 .% find the 100 db column on the right of the table and look down this column for a value greater than or equal to your pass band percentage of the clock rate. then look across to the extreme left column and find the corresponding decimation rate. referring to the table, notice that for a decimation of 4, the frequency having 100 db of alias rejection is 0.071 percent which is slightly greater than the 0.07 percent calculated. there- fore, the maximum bound on cic2 decimation for this condi- tion is four. additional decimation means less alias rejection than the 100 db required. note that although an m cic2 less then four would still yield the requi red rejection, overall power consumption is reduced by decimating as much as possible in this stage. decimation in cic2 lowers the data rate and thus reduces power consumed in subsequent stages. the plot below shows the cic2 transfer function using a deci- mation of four. the first plot is referenced to the input sample rate, the complex spectrum from f samp /2 to f samp /2. the sec- ond plot is referenced to the cic2 output rate, the complex spectrum from f samp2 /2 to f samp2 /2. the aliases of the cic2 can be seen to be folding back in toward the edge of the desired filter pass band. it is the level of these aliases as they move into the desired pass band that are important. 0.5 120 100 80 60 40 20 0 dbfs f/f samp 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 0.5 120 100 80 60 40 20 0 dbfs f/f samp2 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 figure 36. cic2 alias rejection, m cic2 = 4 the set of plots below show a decimation of 16 in the cic2 filter. the lobes of the filter drop as the decimation rate increases, but the amplitudes of the aliased frequencies increase because the output rate has been reduced.
ad6620 C23C rev. a the frequency response of the filter is given by the following equations. the gain and pass band droop of cic5 should be calculated by these equations. both parameters may be compen- sated for in the rcf stage. hz z z s m cic cic () = ? ? ? ? ? ? + 1 2 1 1 5 5 51 5 hf mf f f f s cic samp samp cic () sin sin = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 2 5 5 5 2 2 5 the scale factor, s cic 5 is a programmable unsigned integer between 0 and 20. it serves to control the attenuation of the data into the cic5 stage in 6 db increments. for the best dynamic range, s cic5 should be set to the smallest value possible (lowest attenuati on) without creating an overflow condition. this can be safely accomplished using the equation below, where ol cic2 is the largest fraction of full scale possible at the input to this filter stage. this value is output from the cic2 stage then pipe- lined into the cic5. s cic5 is ignored when this filter is bypassed by setting m cic5 = 1. s ceil m ol ol m ol cic cic cic cic cic s cic cic 525 5 2 5 5 5 5 2 5 2 5 = () = () + log ( ) when cic5 is bypassed; ol ol cic cic 52 = the output rate of this stage is given by the equation below. f f m samp samp cic 5 2 5 0.5 120 100 80 60 40 20 0 dbfs f/f samp 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 0.5 120 100 80 60 40 20 0 dbfs f/f samp2 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 figure 37. cic2 alias rejection, m cic2 = 16 5th order cascaded integrator comb filter the third signal processing stage, cic5, implements a sharper fixed-coefficient, decimating filter than cic2. the input rate to this filter is f samp2 . the maximum input rate is given by the equation below. n ch equals two for diversity channel real input mode; otherwise n ch equals one. in order to satisfy this equation, m cic2 can be increased, n ch can be reduced, or f clk can be increased (reference fractional rate input timing described in the input timing section). f f n samp clk ch 2 2 the decimation ratio, m cic5 , may be programmed from 1 to 32 (all integer values). when m cic5 = 1, this stage is bypassed and the cic5 scale factor is ignored.
ad6620 C24C rev. a this table helps to calculate an upper bound on decimation, m cic5 , given the desired filter characteristics. the plots following (figure 38) represent the cic5 transfer function with respect to the cic5 output rate for a decimation of 4. the first plot is referenced to the input sample rate and shows the complex spectrum from f samp/ 2 to +f samp /2. the second plot is referenced to the cic5 output rate; the complex spectrum ranges from f samp5 /2 to +f samp5 /2. aliased images in cic5 fold back toward the edge of the desired filter pass band. it is the level of these aliases as they move into the desired pass band that are of concern. the improved roll-off of cic5 over cic2 can be seen when these plots are compared to those previously shown for cic2. 0.5 120 100 80 60 40 20 0 dbfs f/f samp 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 0.5 120 100 80 60 40 20 0 dbfs f/f samp5 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 figure 38. cic5 alias rejection, m cic5 = 4 cic5 rejection the table below illustrates the amount of bandwidth in percent- age of the clock rate that can be protected with various decimation rates and alias rejection specifications. the maximum input rate into the cic5 is 32.5 mhz. as in the previous table, these are the 1/2 bandwidth characteristics of the cic5. note that the cic5 stage can protect a much wider band than the cic2 for any given rejection. table iv. ssb cic5 alias rejection table (f samp2 = 1) bandwidth shown in percentage of f samp2 m cic5 ?0 db ?0 db ?0 db ?0 db ?0 db ?00 db 2 10.227 8.078 6.393 5.066 4.008 3.183 3 7.924 6.367 5.11 4.107 3.297 2.642 4 6.213 5.022 4.057 3.271 2.636 2.121 5 5.068 4.107 3.326 2.687 2.17 1.748 6 4.267 3.463 2.808 2.27 1.836 1.48 7 3.68 2.989 2.425 1.962 1.588 1.281 8 3.233 2.627 2.133 1.726 1.397 1.128 9 2.881 2.342 1.902 1.54 1.247 1.007 10 2.598 2.113 1.716 1.39 1.125 0.909 11 2.365 1.924 1.563 1.266 1.025 0.828 12 2.17 1.765 1.435 1.162 0.941 0.76 13 2.005 1.631 1.326 1.074 0.87 0.703 14 1.863 1.516 1.232 0.998 0.809 0.653 15 1.74 1.416 1.151 0.932 0.755 0.61 16 1.632 1.328 1.079 0.874 0.708 0.572 17 1.536 1.25 1.016 0.823 0.667 0.539 18 1.451 1.181 0.96 0.778 0.63 0.509 19 1.375 1.119 0.91 0.737 0.597 0.483 20 1.307 1.064 0.865 0.701 0.568 0.459 21 1.245 1.013 0.824 0.667 0.541 0.437 22 1.188 0.967 0.786 0.637 0.516 0.417 23 1.137 0.925 0.752 0.61 0.494 0.399 24 1.09 0.887 0.721 0.584 0.474 0.383 25 1.046 0.852 0.692 0.561 0.455 0.367 26 1.006 0.819 0.666 0.54 0.437 0.353 27 0.969 0.789 0.641 0.52 0.421 0.34 28 0.934 0.761 0.618 0.501 0.406 0.328 29 0.902 0.734 0.597 0.484 0.392 0.317 30 0.872 0.71 0.577 0.468 0.379 0.306 31 0.844 0.687 0.559 0.453 0.367 0.297 32 0.818 0.666 0.541 0.439 0.355 0.287
ad6620 C25C rev. a the maximum number of taps this filter can calculate, n taps , is given by the equation below. the value n taps minus 1 is writ- ten to the ad6620 internal address space at address 30c hex. the decimation ratio of this filter, m rcf , may be programmed from 1 to 32. the input rate into the rcf is f samp5 . n ch is equal to two for diversity channel real input mode; otherwise n ch = 1. n fm f n taps clk rcf samp ch ? ? ? ? ? ? min , 5 256 the rcf coefficients are located in addresses 0x000 to 0x0ff and are interpreted as 20-bit twos complement numbers. when writing the coefficient ram, the lower addresses will be multi- plied by relatively older data from the cic5 and the higher coefficient addresses will be multiplied by relatively newer data from the cic5. the coefficients need not be symmetric and the coefficient length, n taps , may be even or odd. if the coefficients are symmetric, then both sides of the impulse response must be written into the coefficient ram. the rcf stores the data from the cic5 into a 256 36 ram. 256 18 is assigned to i data and 256 18 is assigned to q data. the rcf uses the ram as a circular buffer, so that it is difficult to know in which address a particular data element is stored. to avoid start-up transients due to undefined data ram values, the data ram should be cleared upon initialization. the rcf utilizes the number of data ram locations equal to n taps n ch , rounded up to the nearest even number, starting from address 0x100, so these are the only values that need be cleared. when the rcf is triggered to calculate a filter output, it starts by multiplying the oldest value in the data ram by the first coefficient (located by the rcf off register in address 0x30b). this value is accumulated with the products of newer data words multiplied by the subsequent locations in the coefficient ram until the coefficient address rcf off + n taps 1 is reached. table v. three-tap filter coefficient address impulse response data 0 h(0) n(0) newest 1 h(1) n(1) 2 (n taps 1) h(2) n(2) oldest the output rate of this filter is determined by the output rate of the cic5 stage and mrcf. f f m sampr samp rcf = 5 rcf coefficient address offset this register at address 30b hex allows the ad6620 to hold multi ple filters in the ram. however, the sum of the taps required may not exceed 256 divided by the number of chan- nels. the rcf will compute the filter from rcf_offset to (rcf_offset + n taps ). a single access can then be used to select which of the filters is used without requiring coefficients be rewritten. the set of plots below (figure 39) represents a decimation of 32 in the cic5 filter. it can be seen that the lobes of the filter drop as the decimation rate increases, but the aliased frequencies increase due to the reduction of the output rate. 120 100 80 60 40 20 0 dbfs f/f samp 0.3 0.2 0.1 0.1 0.2 0.3 0 0.5 120 100 80 60 40 20 0 dbfs f/f samp5 0.4 0.3 0.2 0.1 0.1 0.2 0.3 0.4 0.5 0 figure 39. cic5 alias rejection, m cic5 = 32 ram coefficient filter the final signal processing stage is a sum-of-products decimat- ing fi lter with programmable coefficients. figure 40 shows a simplified block diagram. the data memories i-ram and q-ram store the 256 most recent complex samples from the previous filter stage with 18-bit resolution. the coefficient memory, c-ram, stores up to 256 coefficients with 20-bit resolution. on each clk cycle one tap for i and one tap for q is calculated using the same coefficients. the i and q accumulators provide 3 bits of headroom. this headroom allows the output of the rcf filter to contain 23 significant bits. i in q in i out q out 256 18b i-ram 256 20b c-ram 256 18b q-ram figure 40. ram coefficient filter block diagram
ad6620 C26C rev. a rcf output scale factor the scale factor associated with the rcf, s out , behaves differ- ently than the scale factors in the cic stages. this scalar, at the rcf output, controls the weight of the 16-bit output data going to the parallel port or to the serial port when using 16-bit words. s out determines which of the 23 rcf output bits are used based on the equation below. ol rcf is the 23-bit rcf output data; pol represents the output port data. pol is rounded to the 16 bits desired. the weight of the rounding is adjusted by s out . when the serial port is used with 24-bit or 32-bit words, s out is ignored. pol round ol bits rcf s out = 16 4 2 () ( ) another way to consider the effects of the rcf output scale factor is discussed here. if both cic scalars follow the previous recommendations, the following chart can be used to determine what value to use for the rcf scale factor. in order to determine this, the gain of the impulse response must first be determined. this can be done by integrating the coefficients used for the rcf filter remembering to normalize the values against the full- scale input range of 2 19 . there are several possibilities when setting the gain of the rcf coefficients. following these guidelines will preserve at least three bits in the sum of products registers. 1. hn ( ) = 1 ; 0 db dc gain in rcf filter. numeric wraparound very unlikely. the rcf scale factor should be nominally set to 4. 2. hn ( ) 1 ; slight loss in rcf filter. numeric wraparound is impossible. the rcf scale factor should be nominally set to 4. 3. hn m ( ) = ; where the absolute value of m is a number less than 1 and is scaled to account for losses elsewhere in the system, such as conversion gain errors, attenuator losses or cic scaling errors. the gain should be scaled down to avoid wraparound in the rcf process, however, then the rcf scale factor can be adjusted up to increase the signal level. the value of m can also be negative to account for an inver- sion through an amplifier. the rcf scale factor should be set where needed to produce the desired full-scale results with a fully loaded receiver input signal. the rcf scale factor has the effect as shown in the following table. each successive gain step doubles or halves the overall gain of the stage. overall gain through the rcf stage is the cascaded gain of the rcf scale factor shown below and the rcf coefficient gain discussed previously. table vi. rcf gain rcf scale factor (address 309h) 1/8 7 1/4 6 1/2 5 14 23 42 81 16 0 gain through the rcf of the ad6620 is thus: gain gain coefficients rcf unique b operation unique b works in conjunction with dual channel mode. in this mode, both the a and b channels can have different fir coeffi- cients. this can prove useful in many applications where each signal path has known differences. another option is that fir gain for one path could be different than the other. during diversity selection, one path could be tailored for weak signals and the other for strong signals, providing extra dynamic range. to use the unique b mode, set bit 3 high in register 309h. this will cause the internal state machine to use a different set of coefficients for the b channel than the a. with bit 3 set low for normal operation, the fir coefficient index is incremented only after both the a and b channels are computed. however when this bit is set high, the index is incremented after each a channel and b channel computation. therefore, filters are computed nor- mally. when downloaded to the ad6620, they should be inter- leaved with the a channel terms occupying the even rcf coefficient locations and the b channel terms occupying the odd locations. both filters must be the same length and fit in the allocated memory space. with unique b set to 0, the following table illustrates how the coefficients are distributed. table vii. coefficient address w(0) 0 w(1) 1 w(2) 2 w(3) 3 with unique b set to 1, the following table illustrates how the coefficients are distributed. table viii. coefficient address wa(0) 0 wb(0) 1 wa(1) 2 wb(1) 3
ad6620 C27C rev. a if the ad6620s to be synchronized have identical decimation, then latency through the filter stages will be matched and output data rates for the sync master s filter stages will match the cor- responding filter stages of the slave. sync m/s master slave sync cic sync rcf master slave figure 42. sync_cic, sync_rcf pins the three sync inputs to the control block originate from the same three bidirectional pads from which the three sync out- puts are driven. when the ad6620 is a sync master, the internal circuitry that generates the sync pulse outputs is enabled to the pads. when the ad6620 is a sync slave, the internally produced sync pulses are three-stated, and the pads are driven from an external input. the capacitance on these pins must be closely monitored since the master responds to the same sync pulse as the slave (its own pulse). there is no input requirement to the relative phases of these sync pulses. in the absence of sync pulses each state machine will free run so the latter decimation filters can be reliably synchronized by the sync pulses of an earlier stage. however, when sync pulses are provided externally, setup-and-hold times must be met for each respective input. control registers and on-chip ram the ad6620 provides a choice of two control ports. it has an 8-bit generic microprocessor port that is used for c onfiguring the device at boot up and dynamically reconfiguring the ad6620 in the system. it also has a synchronous serial port that can also dynamically reconfigure the ad6620 for the desired system operation. all control registers are available from both the serial port and the microprocessor port. these control methods are nonexclusive and the two ports can be used simultaneously. if simultaneous access occurs, the serial port is given precedence over the microprocessor port unless a micro cycle is already under way. the microprocessor port deasserts the rdy signal and waits until the serial access is completed for mode 0. the microprocessor port does not assert dtack for mode 1 until the serial access is completed. filter phase synchronization like the nco, the ad6620 filter stages have phase synchroni- zation circuitry enabling multiple ad6620s to be used in appli- cations such as diversity antennas and phased array systems. for any f samp , there are m cic2 possible phases of f samp2 at the output of the cic2 stage. similarly, at the output of the cic5 stage, there are m cic5 possible phases of f samp5 . this means that at the output of the cic stages there is already m cic2 m cic5 possible phases of the filtered data. additional phase uncertainty is introduced by decimation done in the rcf. at the output of the ad6620 there are a total of m cic2 m cic5 m rcf possible output phases of the data. in diversity systems using multiple ad6620s, it is necessary to ensure that the output of each ad6620 in the system is in phase. a variety of system issues (e.g., not bringing the ad6620s on line at the same time, excessive digital noise) could cause the ad6620s to start out-of-phase or to drift out-of-phase as the system runs. to achieve output phase coherence in such systems the sync_cic and sync_rcf pins are provided. the function of these pins is controlled by the sync_m/s bit in the mode control register at address 300 hex of internal address space. when the sync_m/s bit is high, sync_cic and sync_rcf provide synchronization pulses on the rising edge of clk. when the sync_m/s bit is low, sync_cic and sync_rcf accept external synchronization pulses sampled on the rising edge of clock. this pulse edge synchronizes the cic2, cic5 and rcf filter stages of all ad6620 in the chain. below is an example of the output sync pulse waveforms. the s ync_nco pulse is not shown and is described in the preceding nco synchronization section. each sync_rcf output pulse is concurrent with a sync_cic pulse. the sync_rcf output pulse can be connected to the sync_cic, and sync_rcf inputs of another ad6620 to achieve full decimation synchronization. clk sync cic sync rcf figure 41. sync output pulses in the example above, m cic2 = 3, and m cic5 = 1 as evidenced by the sync_cic pulses that occur every 3 clk cycles (m cic2 m cic5 ). m rcf = 3, resulting in sync_rcf pulses that are one third as frequent as the sync_cic pulses. in this example full rate input timing is employed such that the input data rate equals the clock rate.
ad6620 C28C rev. a table ix. control register and ram addresses address bit width name notation description 000 0ff 20 rcf coefficient ram rcf coefficient ram 100 1ff 36 rcf data ram rcf data ram 200 27f 0 reserved reserved 300 8 mode control register 0: soft_reset 1 1: diversity channel real input mode 2: single channel complex input mode 3: sync master/slave 2 (master = 1, slave = 0) 7 4: reserved 301 3 nco control register 0: nco bypass (bypass = 1, active = 0) 1: enable phase dither 2: enable amplitude dither 7 3: reserved 302 32 nco sync control register sync_mask write: sync mask shadow read: sync mask 303 32 nco_freq nco_freq channel frequency for nco tuning 304 16 nco phase_offset nco phase offset 305 8 input/cic2 scale register 2 0: s cic2 3: reserved 4: expinv 7 5: : expoff 306 8 m cic2 1m cic2 1 cic2 decimation minus one 307 5 cic5 scale register s cic5 4 0: s cic5 7 5: reserved 308 8 m cic5 1m cic5 1 cic5 decimation minus one 309 4 output/rcf control register s out 2 0: output scale factor 3: unique b flag (normal mode = 0, unique b mode = 1) 7 4: reserved 30a 8 m rcf 1m rcf 1 rcf decimation minus one 30b 8 rcf address offset register rcf off filter coefficient address offset 30c 8 n taps 1n taps 1 number of taps minus one 30d 8 reserved (should be written 0) reserved (should be written 0) notes 1 this bit is set high on reset . the chip is held into soft_reset until it is written low. 2 this bit is set low on reset . this keeps multiple ad6620 sync masters from driving each other. outputs while acting as a sync master, or as inputs while acting as a sync slave. this is the only register with a defined power-up state: on power-up, bit 0 will be at a logic 1. this places the chip in soft_reset and defines the chip as a sync slave. powering up as a sync slave avoids contention problems when connecting multiple ad6620s. if bit 0 is written low and bits 2 and 1 are low, the ad6620 is in single channel real mode. if bit 1 is high and bits 0 and 2 are low, the device is in the diversity channel real mode. if bit 2 is high and bits 0 and 1 are low, the chip is in the single chan- nel complex mode. setting bit 3 high configures the ad6620 as a sync master; the sync pins are then used as outputs. if bit 3 is low, it is a sync slave and the sync pins function as inputs. bits 7 4 are reserved and should be written low. (0x301) nco control register this register allows control of special features of the nco. if bit 0 of this register is high the nco of the ad6620 is by-passed. both the i data and the q data that are passed through the chip will be the same and the spectrum will not be translated. in bypass the input data is attenuated by 12 db. (0x000?xff) rcf coefficient ram memory that stores user-programmable coefficients for the rcf filter. the ram will hold 256 20-bit twos complement words for a maximum filter length of 256 taps. in diversity channel real mode the filter length is limited to 128 taps per channel. the number of taps used is controlled by n taps 1 (30c) regard- less of the number of coefficient locations programmed. if filter size allows, more than one filter can be resident in the memory at a time. this makes it possible to switch filters without re loading all of the coefficients. (0x100?x1ff) rcf data ram these locations store i and q data exiting the cic5 filter stage while the rcf performs multiply accumulates. the lower 18 bits of the 36-bit location is i data; the upper 18 bits are q data. these locations are addressed in memory and are available via the control ports so that the data ram can be flushed for test- ing and simulation purposes. they are not cleared on reset. (0x300) mode control register this location brings the chip out of reset and sets the operating mode. it also specifies how the chip will use its sync pins: as
ad6620 C29C rev. a (0x309) output/rcf control register bits 2-0 of this register hold the output scale factor, s out . these bits are interpreted as a 3-bit unsigned integer, the value of which controls which of the 23 output bits of the rcf are passed to the output port being used. the data output corre- sponds to the following equation where ol rcf is the 23-bit output of the rcf and pol is the 16-bit data available at the parallel output port or the serial port when 16-bit serial words are used. the truncation function rounds the scaled 23-bit number to 16 bits. s out is ignored when wl is 24 or 32 bits. in most applications, this register should be set to 4 as an initial starting value. pol round ol bits rcf s out = 16 4 2 () ( ) for additional details on determining rcf gain, see the rcf output scale factor section. bit 3 of this register is used to control the unique b feature of the chip. when written low, the normal mode, the chip uses the same fir coefficients for both the a and b channels. however, when the bit is set high, different coefficients are used for the a and b channels. when unique b mode is selected, the filter coefficients should be interleaved with the a channel terms occupying the even rcf coefficient locations and the b chan- nel terms occupying the odd locations. bits 7 4 of this register are reserved and must be written 0. (0x30a) (m rcf ?1) this register controls the amount of decimation in the rcf filter stage. the value contained in this register is the rcf decimation rate minus one. this is interpreted as an unsigned 8-bit integer, but due to limited number of taps and, therefore, filtering power in the rcf filter accumulators this value should be limited to 31 (decimation = 32). (0x30b) rcf address offset register this register controls the address offset used by the rcf to calculate a given filter and is interpreted as an 8-bit unsigned integer. it allows more than one filter to be placed in the coeffi- cient ram. this makes it possible to switch filters without reloading all of the coefficients. the rcf filter will compute taps for all coefficients between rcf off and (rcf off + n taps ) provided that the decimation, clk rate and input data rate provide sufficient time for this. (0x30c) (n taps ?1) this register controls the number of taps calculated by the rcf. the value in this register is interpreted as an unsigned integer and is equal to the number of taps desired minus one. this filter is not inherently symmetric and the number of coefficients placed in the coefficient ram will be equal to the number of t aps, provided that only one filter at a time is loaded. no symmetry is assumed and preaddition is not used. the total number of taps for all filters must be less than 256 taps for single channel real mode, or less than 128 taps/channel for diversity channel real mode. (0x30d) reserved reserved, but must be written 0 for correct operation. the nco has two features to improve the performance of some systems: phase dither and ampli tude dither. these can be used together or alone. if bit 1 of the register is high, phase dither is activated. if bit 2 is high, amplitude dither is activated. for more information on dither refer to the nco section. (0x302) nco sync control register this holds the sync_mask, which controls the frequency of the sync_nco pulses and therefore the phase accuracy of the synchronization. see the nco section for details. (0x303) nco_freq this register holds the nco frequency control word as described in the nco section. this is a 32-bit unsigned integer that sets the frequency of the ad6620 nco. (0x304) nco phase_offset this regi ster controls the phase offset of the nco. it is also described in detail in the nco section and can be used to allow for phase differences between multiple antennas receiving the same carrier. (0x305) input/cic2 scale register this register holds the scale factor, s cic2 , for cic2. s cic2 scales down the data before it is accumulated in cic2. t his avoids register wrap-a round in the twos-complement arithm etic and eliminates the resulting spectral errors. s cic2 is contained in bits 2 0 of this register. it is treated as an unsigned integer between 0 and 6. increasing s cic2 shifts data down. for more det ails refer to the section on the cic2 filter. the second function of this register is to scale the input data from the parallel data input port. this allows the ad6620 to treat the floating point input data with considerable flexibility. there are two parts of this function. the first is bit 4, w hich tells the ad6620 how to handle the exponent, exp[2:0]. if this bit is low, data is shifted down as the exponent increases. if this bit is high, then for increasing exp[2:0] the input data is shifted up. the second part of the input data shifting is the exponent offset(expoff[7 . . 5]) held in bits 7 5 of this register. this pro- vides gain to the input data as described in the input port section. (0x306) (m cic2 ?1) this register controls the amount of decimation in the cic2 filter stage. the value contained in this register is the cic2 decima- tion rate minus one. this is interpreted as an unsigned 8-bit integer but due to limited growth in the cic2 filter accumula- tors this value should be limited to 15 (decimation = 16). (0x307) s cic5 this register holds the scale factor, s cic5 , for cic5. s cic5 scales down the data before it is accumulated in cic5. this avoids register wrap-around in the twos-complement arithmetic and elimi- nates the resulting spectral errors. s cic5 is contained in bits 4 0 of this register. it is treated as an unsigned integer between 0 and 20. increasing s cic5 shifts data down. for more details refer to the section on the cic5 filter. (0x308) (m cic5 ?1) this register controls the amount of decimation in the cic5 filter stage. the value contained in this register is the cic5 decimation rate minus one. this is interpreted as an unsigned 8-bit integer, but due to limited growth in the cic5 filter accu- mulators this value should be limited to 31 (decimation = 32).
ad6620 C30C rev. a programming the ad6620 initializing the ad6620 before the ad6620 can be used to down convert and filter the channel of interest it must be configured for the job. first the reset pin should be pulsed low for a minimum of 30 ns and should then be returned high. this hard_reset of the ad6620 clears the cic accumulators as well as the nco phase accumulator. when reset is brought high the ad6620 is removed from the hard_reset condition. the ad6620 is now in soft_reset. in this state the mode control register at address 0x300 contains a 1 (bit 0 is high). when the ad6620 is in soft_reset, no data is accepted by the input data port and no pro cessing occurs. the serial port and par allel output port is held inactive and the chip is defined as a sync slave to avoid possible contentions on these pins. while the ad6620 is in this condition it should be programmed by the process below. it should be noted that this initialization must be performed via the microprocessor port since the serial port is inactive. 1. if the ad6 620 is being reinitialized without performing a hard_reset, then address 0x300 should be written 1 to place the ad6620 in soft_reset. this allows the non- dynamic registers to be programmed. 2. program the coefficient ram of the ad6620 with the desired fir f ilter. the address auto-increment feature can be used to decrease the amount of time required to program the coefficients. this feature is described in detail in the microp ort control section that follows. 3. (optional) the first piece of data out of the ad6620 is always zero due to an output pipeline delay. there will also be a start-up glitch on the output of the ad6620 due to possible nonzero data in the i and q data rams of the rcf filter. these rams are not initialized by the hard_reset. if this is a concern then the data rams should now be written to zero. for efficiency the auto-increment feature can be used as with the programming of the coefficient rams. 4. the configuration registers of the ad6620 are now pro- gramm ed. first, address 0x300 should be written to set the operating mode if diversity channel real or single channel complex modes are used. bit 0 of this register should remain high at this time. this will hold the soft_reset condition. the remaining configuration registers can now be programmed. this should start at address 0x301 and continue to address 0x30d. this defines the operation of the nco and filter stages. 5. the ad6620 is now ready to be removed from soft_reset and allowed to process data. this is done by writing address 0x300 to again set the desired mode of operation. this loca- tion should be set for sync master or s ync slave operation at this time. bit 0 of this register is written low at this time to remove the soft_reset condition. dynamic programming of the ad6620 many attributes of the ad6620 may be altered dynamically as the ad6620 processes the received data. this allows the receiver to be adjusted during operation in order to achieve the maxi- mum performance. the typical dynamic registers of the ad6620 are listed in the following table. to program the other registers follow the steps described in the section titled initializing the ad6620. technically all registers can be programmed dynami- cally, but adverse results may occur if registers other those listed are written dynamically. these addresses may be programmed via either the micropro- cessor or the serial control ports. table x. dynamic ad6620 registers address bit width name 302 32 nco sync control register 303 32 nco_freq 304 16 nco phase_offset 305 8 input/cic2 scale register 307 5 cic5 scale register 309 4 output/rcf control register 30b 8 rcf address offset register registers 0x302, 0x303 and 0x304 allow the nco of the ad6620 to be adjusted. the tuning frequency can be dynamically changed for frequency hopping. the phase of the carrier can be adjusted with address 0x304. the phase accuracy of the synchronization can be changed with 0x302. registers 0x305, 0x307, and 0x309 allow the user to dynamically control the gain of the ad6620 in 6 db increm ents. this can be used to m aximize the ad6620s dynamic range for the signal being tuned at a particular instant. register 0x307 allows for agc where the dsp does power spectral estimation. in addition to dynamically writing to these registers, they may also be read to verify program content. care should be taken, however, because reading some registers may affect normal chip operation. in particular, reading from 303h the nco frequency will cause the phase accumulator to be reset via the sync_nco pulse if the ad6620 is running as a sync master. if the device is run as a sync slave, then the phase accumulator is not reset. addresses 000h through 1ffh should not be read dynamically as doing so will disrupt the internal state machine computing the fir taps. these locations may be read statically if needed.
ad6620 C31C rev. a access protocols the ad6620 external accesses may be performed through either the microprocessor port or the serial port. the microport and the serial port both use a three-bit address and eight-bit data to access these registers. the three-bit address provides access to seven register locations (external interface registers). these register locations are used to access the internal address space of the ad6620 shown in the control register section. the seven registers are the lar (low address register), the amr (address mode register), and the five data registers (dr4 dr0). table xi. external interface registers a[2:0] name comment 000 data register 0 (dr0) d[7:0] 001 data register 1 (dr1) d[15:8] 010 data register 2 (dr2) d[23:16] 011 data register 3 (dr3) d[31:24] 100 data register 4 (dr4) d[35:32] 101 reserved reserved 110 low address register (lar) a[7:0] 111 address mode register (amr) 1-0: a[9:8] 5-2: reserved 6: read increment 7: write increment the internal address space is accessed using a 10-bit internal address. many of these address locations are more than a byte wide and require multiple accesses to the seven external inter- face registers, which are each only 8 bits wide (only 4 bits of dr4 are used). accesses to these registers are accomplished using the 3-bit address and 8-bit data lines the manner described below. the source of these values depends on the control port method used. all internal accesses are accomplished by first writing the inter- nal address of the register or memory location to be accessed. the lower eight address bits are written to the lar register and the upper two address bits to the lsbs of the amr. this defines the internal address of the location to be accessed as shown in the memory map shown in the control registers and on-chip ram section. internal write access up to 36 bits of data (as needed) can be written by the process described below. any high order bytes that are needed are writ- ten to the corresponding data registers defined in the external 3-bit address space. the least significant byte is then written to dr0 at address (000). when a write to dr0 is detected, the internal microprocessor port state machine then moves the data in dr4 dr0 to the internal address pointed to by the address in the lar and amr. write pseudocode void write_micro(ext_address, int data); main(); { / * this code shows the programming of the nco frequency register using the write_micro function as defined above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. the nco register is located at internal address = 0x303 * / // holding registers for nco byte wide access data int d3, d2, d1, d0; // nco frequency word (32-bits wide) nco_freq = 0xcbefefff; // write amr write_micro(7, 0x03); // write lar write_micro(6, 0x03); // dr4 is not needed because nco_freq is only 32-bits, not 36 // write dr3 with high byte of 32 bit word (d[31:24] d3 = (nco_freq & 0xff000000) >> 24; write_micro(3, d3); // write dr2 with high byte of 32 bit word (d[23:16] d2 = (nco_freq & 0xff0000) >> 16; write_micro(2, d2); // write dr1 with d[15:8] d1 = (nco_freq & 0xff00) >> 8; write_micro(1, d1); // write dr0 with d[7:0] // writing to dr0 causes all data to be transferred to the internal address. //therefore, dr1, dr2 and dr3 should already be written d0 = nco_freq & 0xff; write_micro(0, d0); } // end of main internal read access a read is performed by first writing the lar and amr as with a write. the data registers (dr4 dr0) are then read in the reverse order that they were written. first, the least significant byte of the data (d[7:0]) is read from dr0. on this transaction the high bytes of the data are moved from the internal address pointed to by the lar and amr into the remaining data regis- ters (dr4 dr1). this data can then be read from the data registers using the appropriate 3-bit addresses. the number of data registers used depends solely on the amount of data to be read or written. any unused bit in a data register should be masked out for a read.
ad6620 C32C rev. a read pseudocode int read_micro(ext_address); main(); { / * this code shows the reading of the nco frequency register using the read_micro function as defined above. the variable address is the external address a[2..0] and data is the value to be placed in the external interface register. the nco register is located at internal address = 0x303. * / // holding registers for nco byte wide access data int d3, d2, d1, d0; // nco frequency word (32-bits wide) // write amr write_micro(7, 0x03 ); // write lar write_micro(6, 0x03); / * read d[7:0] from dr0, all data is moved from the internal registers to the interface registers on this access. reading should be initiated with a read from dr0. therefore, dr1, dr2 and dr3 can be read after dr0 * / d0 = read_micro(0) & 0xff; // read d[15:8] from dr1 d1 = read_micro(1) & 0xff; // read d[23:16] from dr2 d2 = read_micro(2) & 0xff; // read d[31:24] from dr3 d3 = read_micro(3) & 0xff; // dr4 is not needed because nco_freq is only 32-bits // assemble 32-bit nco_freq word from the 4 byte components nco_freq = d0 + (d1 << 8) + (d2 << 16) + (d3 << 24); } // end of main auto increment feature to increase throughput, an auto increment feature is provided. this feature is controlled by bits 6 and 7 of the amr. if these bits are set to 00, the address remains the same after an internal access. if set to 01, the address is incremented after a read access has been pe rformed. if set to 10, the address is incremented after a write access is performed. if set to 11, the address is incre- mented a fter each access, read or write. this allows the ad6620 to be initialized in a much shorter time since the access to the lar and amr must occur only once to initialize or read-back the entire device. microport control external reads and writes are accomplished in one of two modes via the microprocessor port. the cs , rd ( ds ), rdy ( dtack ), wr (r/w) and mode pins are used to control the access. the specific function of these pins depends on whether the access is mode 0 or mode 1. the mode 1 signal names are those listed on the pinout. the access mode is controlled by the mode input as described in the following sections. table xii. microprocessor control signals mode 0 mode 1 a[2:0] (address lines) a[2:0] (address lines) d[7:0] (data lines) d[7:0] (data lines) cs (chip select) cs (chip select) rd (read strobe) ds (data strobe) wr (write strobe) r/w (read/write select) rdy (ready signal) dtack (data acknowledge) mode (mode select) mode (mode select) the microport is synchronous with the master clock (clk) of the ad6620, but the interface is not required to be. if the speed of the interface is significantly slower than clk, synchronicity should not be an issue. if the interface is relatively fast com- pared to clk, the user may need to synchronize the microport to clk or add wait states to the controlling processor. the timing diagrams show the relationship of the control signals to clock and the user should use these as a guide to implement a microport interface.
ad6620 C33C rev. a mode = 0 if mode is low during the access, the interface is in mode 0. in mode 0 the cs , rd and the wr lines control the access type. while an access is being performed, or if the serial port data valid t hc t sc t hc t sc t hm address valid n n+1 n+2 n+3 n * clk 1 wr 2 rd 2 cs 3 d[7:0] rdy a[2:0] notes: 1 rdy is driven low asynchronously by wr and cs going low and returns high on the 2 these signals (r/w and ds ) may remain in low state to continue writing data. 3 cs must return to high state and be sampled by clk (n+3 shown) to complete write. * the next write may be initiated on clk, n. t ha t rdyh t rdyl t sam t sam rising edge of clk "n+2". figure 44. mode 0 write (mode = gnd) is accessing the chip, the rdy line goes low at the start of the access. when the internal cycle is complete the rdy line is released. t dd data valid t hc t sc t hc t zd t ha t rdy t rdy address valid t sam t zr n n+1 n+2 n+3 n+4 n clk 1 wr 2 rd 2 cs 3 d[7:0] rdy 1 a[2:0] notes: 1 rdy is driven low asynchronously by rd and cs going low and returns high on the rising edge of clk "n+3" for internal access (a[2:0] = 000), clk "n+2" otherwise. 2 the signal, wr , may remain high and rd may remain low to continue read mode. 3 cs must return to high state and be sampled by clk (n+4 shown) to complete read. figure 43. mode 0 read (mode = gnd)
ad6620 C34C rev. a data valid t sc address valid n n+1 n+2 n+3 clk 1 r/w 2 ds 2 cs 3 d[7:0] dtack a[2:0] t sam n+4 n t hc t dd t hc t zd t ha t dtack t dtack notes: 1 dtack is driven low on the rising edge of clk "n+3" for internal access (a[2:0] = 000), clk "n=2" otherwise. 2 the signal, r/w may remain high and ds may remain low to continue read mode. 3 cs must return to high state and be sampled by clk (n+4 shown) to complete access and force dtack high. t sc t zr figure 45. mode 1 read (mode = vdd) mode = 1 if the mode input is held high the interface is in mode 1. in mode 1 the rd signal becomes the data strobe ( ds ) and the wr signal becomes a read/write (r/w) select signal. in this t sc n n+1 n+2 n+3 t sam n * t dtack t sc clk 1 r/w 2 ds 2 cs 3 d[7:0] dtack a[2:0] t hc t hc t dtack t sam t hm t ha notes: 1 on rising edge of "n+3" clk, dtack is driven low. 2 these signals (r/w and ds ) may remain in low state to continue writing data. 3 cs must return to high state and be sampled by clk (n+3 shown) to complete write and force dtack high. * the next write may be initiated on clk , n * data valid address valid figure 46. mode 1 write (mode = vdd) mode the dtack signal goes low when data is available during a read or when data has been latched during a write. the dtack signal stays low until the ds signal is released.
ad6620 C35C rev. a the data is contained in the low byte of the 16 significant bits. this data will be placed into the external interface register pointed to by a[2 . . 0] for a write and will be ignored for a read. serial port writes if the write bit is high and the read bit is low then a write access is performed to the external interface register pointed to by a[2 . . 0]. a write to an internal register takes place by first writing the amr and lar. the data registers dr4 dr1 are then written as needed. a final write to dr0 then moves the data to the internal register. serial port reads if the read bit is high, then a read to the register indicated is performed and the data will appear in the rdata word appended to the serial frame. the internal data read is loaded into the serial data word in fifo fashion. the first byte read is loaded into the first eight bits, the second read during the frame is loaded into the second byte, etc. since the serial data is shifted msb first, the first byte will actually be loaded into the most significant byte of the serial data word. during a frame (the period between sdfs rising edges) up to four reads may occur. when a read is requested through the serial port, a data word is appended to the end of the serial string. even if ad is not asserted (see below for ad description) a word is added to the end of the iq data stream. therefore, if the chip is in single channel mode, the i and q data are sent f ollowed by a read word. if the chip is in diversity channel mode, the iq pairs are followed by a read word. thus the serial port responds with either three or five serial words in a frame, respectively. if ad is asserted, the read word is sent each frame regardless of a request. if no requests are made, the appended word is all zeros. the number of reads accomplished in a frame is limited by the serial word length. if the serial word length is 16 bits, only two reads can be performed during a frame. if the serial word length is 24 bits, three reads can occur in a frame. if the serial word length is 32 bits, then up to four reads can occur in a frame. the rdata word format is shown below. rows three and four will not be present when 16-bit words are used, and row four will not be present when 24-bit words are used. table xv. rdata word definition da7 da6 da5 da4 da3 da2 da1 da0 db7 db6 db5 db4 db3 db2 db1 db0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 dd7 dd6 dd5 dd4 dd3 dd3 dd1 dd0 the number of words in the serial frame depends on the operat- ing mode of the chip (one or two i/q pairs) and whether or not a read access occurs. it also depends on the append data pin, ad. when this signal is asserted, then the rdata word is appended to the serial frame regardless of whether or not a read was performed in the frame. this allows time-slotted sys- tems where multiple ad6620s or other devices share a serial port of a dsp without hardware handshakes. when ad is high and there has not been a read during the active frame, the rdata word is driven low and sdfe is held off for another serial word length. at all times, the serial interface must have time to shift all bits. the section below serial port guidelines should be consulted to determine if sufficient time exists. serial port control in addition to providing access to the complex output data stream of the ad6620, the serial port can also be used for dynamic control of the device. the dynamic registers of the ad6620 that are typically programmed while the chip is processing are listed in the table below. in order to use the serial port control, the chip must first be booted using the microprocessor interface. table xiii. dynamic registers bit address width name 300 8 mode control register 302 32 nco sync control register 303 32 nco_freq 304 16 nco phase_offset 305 8 input/cic2 scale register 307 5 cic5 scale register 309 4 output/rcf control register 30b 8 rcf address offset register the internal address and data structure are shared between the microprocessor port and the serial port. when accessing the internal ram or registers, the serial port is given priority over a microprocessor request. if a mode 0 access occurs on the microport while the serial port is accessing the internal address space, the rdy line will go low and stay low until the serial access has been completed. if a mode 1 access occurs on the microport during a serial access, the dtack signal will not go low until the serial access has been completed. the microport is used for booting the ad6620 and either the microport or the serial port can be used to dynamically change the system param- eters. both ports may be used in the same design provided that the handshaking rules described above are observed. for each word shifted out of the serial port there is a word shifted in. each input word can provide one internal access. each access can be a read or a write. all reads and writes are per- formed via the same 8-bit registers used by the microprocessor port. each bit in the sdi words has a predefined meaning and are used to decode which of these registers are being accessed and whether the access is a read or a write. the bits are defined according to the table below. table xiv. sdi input word definition read write xxxa2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 x x xxxxxx x x xxxxxx only the first 16 bits of the sdi word contain significant data regardless of the serial word length. the first two bits shifted in are the read and write indicator signals. these bits control the access type as described below and should not be asserted simultaneously. if the serial port is not used for control then the sdi pin should be tied low to disable register reads and writes. the three address bits are the three least significant bits of the upper byte in the 16-bit word. these three bits a[2:0] define which of the seven external registers are accessed by the serial port according to table xi.
ad6620 C36C rev. a example of serial port w/r operation the example shown below demonstrates writing and reading from the ad6620. for this example, the chip is set up in diver- sity channel real mode. therefore, there four data words (two is and two qs) are generated as receiver data. thus four commands can be shifted into the sdi port. these are shown below. addi- tionally, the chip is configured with a word length of 16 bits. the ad6620 response with five words per frame (two is, two qs and the appended read word). table xvi. sdi data format a-i a-q b-i b-q append sdo xxxx xxxx xxxx xxxx 0axx sdi 4703 4600 80xx 4603 xxxx the table above shows the serial output bits for this configura- tion. as the i and q data are being shifted out, the sdi pin is telling the chip what data to return during the appended data field. during the a-i portion of the frame, the hex word 4703 is shifted i nto the chip. breaking this word down, the command instructs the ad6620 to write an 03 into the amr register. the next word, 4600, writes a 00 into the lar. therefore, the chip is so configured that the next command will either read from or write to internal memory space 300 hex, the mode control register. the next word on the sdi pin is 80xx. this indicates a read from dr0. note that the second half of the read word is ig nored. during the b-q word, another read or write can be set up. in this case, 4603 changes the internal memory to point to 303, the nco frequency, thus setting up subsequent access of this register. now during the append data frame, the ad6620 sends any read words that are pending due to read requests. in this case, the contents of register 300. since the chip is in single channel complex mode and running, the chip responds with 0axx. 0a indicates that the chip is in diver- sity channel real mode and running as a sync master. the xx is indeterminate and would have been the results of a second read if one had been requested. par/ser the serial port shares pins with a parallel output port. these pins are arbitrated by the par/ser pin. in order to operate the chip with the parallel output data port par/ser must be high while reset is brought high. for serial port operation, par/ ser must be held low while reset is brought high. par/ser should remain valid while the ad6620 is processing (should only be changed in reset ). par/ser should be hardwired on a given design. sbm serial bus master. when sbm is high, the ad6620 generates sclk and sdfs. when sbm is low, the ad6620 accepts external sclk and sdfs signals. when configured as a bus master the sclk signal can be used to strobe data into the dsp interface. when used with another ad6620 in serial cascade mode, sclk can be taken from the master ad6620 and used to shift data out from the cascaded device. in this situation sdfs of the cascaded ad6620 is connected to the sdfe pin of the master ad6620. when an ad6620 is in serial cascade mode, all of the serial port activities are controlled by the external signals sclk and sdfs. regardless of whether the chip is a serial bus master or is in serial cascade mode, the ad6620 serial port functions are identical except for the source of the sclk and sdfs pins. sclk sclk is an output when sbm is high; sclk is an input when sbm is low. in either case the sdi input is sampled on the falling edge of sclk, and all outputs are switched on the rising edge of sclk. the sdfs pin is sampled on the falling edge of sclk. this allows the ad6620 to recognize the sdfs in time to initiate a frame on the very next sclk rising edge. the m axi- mum speed of this port is 33.5 mhz or half of the master clk signal, whichever is lower. care should be taken with this signal. even when the ad6620 is selected as a serial bus master, reflec- tions on this line will cause the output shifters to double shift output data causing corrupt serial data. if this signal is going to a back plane of more than several inches, the line should either be buffered or be matched to the impedance of the back plane. see the applications section of this data sheet for information on driving the transmission lines. sdi serial data input. serial data is sampled on the falling edge of sclk. this pin is used to write the internal control registers of the ad6620 or to write the address of an internal location to be read. these activities are described later in the serial frame structure section. if this pin is not used to write data into the control port it should be tied low. sdo serial data output. serial output data is switched on the rising edge of sclk. on the very next sclk cycle after an sdfs, the msb of a channel: i data is shifted. on every subsequent sclk edge a new piece of data is shifted out on the sdo pin until the last bit of data is shifted out. the last bit of data shifted is a channel: q data in either of the single channel modes or the b channel: q data in the diversity channel real data. sdo is three-stated when the serial port is outside its time-slot. this allows the ad6620 to share the sdi of a dsp, with other ad6620s. in order to ensure that the three-state condition of this pin does not cause a problem there should either be a bus holder on this signal or there should be a weak pull-down resistor placed on it. this will ensure that the sdo pin is always in a valid logic state. sdfs sdfs is the serial data frame sync signal. sdfs is an output when sbm is high; sdfs is an input when sbm is low. sdfs is sampled on the falling edge of sclk. when sdfs is sampled high, the ad6620 serial port will become active on the next rising edge of sclk for a complete serial time-slot. when sbm is high sdfs will pulse high for one sclk cycle before an active serial time-slot is to be initiated and a transfer will begin immediately on the next rising edge of sclk. when used as a serial slave, the sdfs pin must not receive more than one sdfs per frame. as with sclk, care should be taken with this signal. even when the ad6620 is selected as a serial bus master, reflec- tions on this line can cause erratic framing results. if this signal is going to a back plane of more than several inches, the line should either be buffered or be matched to the impedance of the back plane. see the applications section of this data sheet for information on driving the transmission lines. sdfe serial data frame end output. sdfe will go high during the last sclk cycle of an active time-slot. the sdfe output of a master ad6620 can be tied to the input sdfs of an ad6620 in serial cascade mode in order to provide a hardwired time-slot scenario. when the last bit of sdo data is shifted out of the
ad6620 C37C rev. a master ad6620, the sdfe signal will be driven high by the same sclk rising edge that this bit is clocked out on. on the falling edge of this sclk cycle, the cascaded ad6620 will sample its sdfs signal, which is hardwired to the sdfe of the master. on the very next sclk edge, a channel: i data of the cascaded ad6620 will start shifting out of the port. there will be no rest between the time-slots of the master and slave. wl[1:0] wl defines the word length of the serial data stream. the possible options are 00 16 bit words, 01 24 bit words, 10 32 bit words and 11 undefined. this setting controls the width of all serial words. all words are shifted msb first and are left justi fied, i.e., the first n-bits are valid and any padding that is needed to fill the word length is added at the end. when the serial word length is 24 or 32 bits, the i and q output data is presented with 23-bit resolution. table xvii. setting serial word length serial word length wl1 wl0 16-bit 0 0 24-bit 0 1 32-bit 1 0 disallowed 1 1 ad append data signal. in single channel real mode, when ad is low the serial data stream consists only of a channel: i and q data. if the ad6620 is in diversity channel real mode, the serial frame is four words long and consists of both a and b channel complex data. when the ad signal is high, an extra serial word is appended to the serial frame. this word consists of any data that is read from the ad6620 internal registers via the serial port. if a read has not occurred, the data in this word is zero. the addition of this word allows a serial system to be designed so that any ad6620 can have data read at any time without changing the fixed timing of the serial port. if the serial transfer includes a register read, the register data is appended to the serial frame regardless of the state of the ad pin. sdiv[3:0] when the ad6620 is used as a serial bus master the chip gen- erates a serial clock by dividing down the clk signal. the divider ratio is set by the serial division word, sdiv. sdiv is interpreted as a 4-bit unsigned integer and determines the fre- quency of the serial clock when the sbm pin is pulled high. when the ad6620 is in serial cascade mode these bits are ignored. the following equations express the serial clock fre- quency as a function of the clk signal and the sdiv nibble. f f sdiv f f sdiv sdiv sclk clk sclk clk == = 2 0 2 0 , , serial port guidelines the serial clock, sclk, must be run at a rate sufficient to clock all of the serial data out of the port before new data is latched into the internal i and q data registers. see the serial output data port section for more details. if the serial port is to be used as a means of programming the part, some extra serial bandwidth may also be required to shift data from the internal registers of the ad6620. there must be two or more or zero high speed clocks between serial frames. when used as a serial bus master sclk can run at a maximum rate of half the processing clk. in serial slave mode, the serial clock can be run up to 67 mhz. the equations below help determine what the minimum serial clock rate must be in order to insure that data is not lost. f fwl nr m mmmm sclk samp ch d tot tot cic cic rcf + = () 2 25 r d = 1 if ad is asserted or if read operations are used from the serial port: otherwise r d = 0. this term accounts for the band- width consumed when data is read from the internal control registers or memory. jtag boundary scan the ad6620 supports a subset of ieee standard 1149.1 specifications. for additional details of the standard, please see ieee standard test access port and boundary-scan archit ecture, ieee-1149 publication from ieee. the ad6620 has five pins associated with the jtag interface. these pins are used to access the on-chip test access port (tap) and are listed in the table below. table xviii. pin name description trst tap reset tclk test clock tms tap mode select tdi test data input tdo test data output the ad6620 supports four op codes as shown below. these instructions set the mode of the jtag interface. table xix. instruction op code idcode 01 bypass 11 sample/preload 10 extest 00 the vendor identification code can be accessed through the idcode instruction and has the following format. table xx. msb lsb version part number manufacturing id # mandatory 0000 0010 0111 0111 1110 000 1110 0101 1 a bsdl file for this device is available from analog devices, inc. contact analog devices, inc. for more information.
ad6620 C38C rev. a applications evaluation board an evaluation board is available for the ad6620. this evalua- tion board comes complete with an ad6620 and interfaces to a pc through the printer port. the evaluation board comes com- plete with software to drive the evaluation board and to design optimized filters for use with the ad6620. the evaluation board includes a high speed data interface that mates directly with evaluation boards for high performance converters such as the ad6600 and ad6640, allowing digital receivers to be bread- boarded with only an external rf/if converter and an interface to the dsp. the control software allows access to all of the internal registers to provide complete programming of the device in a lab setting. the software can process high speed data as well as digitally filtered data from the ad6620 allowing analysis of both pre and post filter channel characteristics. the controlling software can also be used to verify the filter performance by sweeping the nco, greatly simplifying verification of any given filter design. ad6620 hi speed data header latch fifo pc printer port latch latch latch transceiver figure 47. evaluation board block diagram as shown in the block diagram below, the high speed data into the evaluation board is sent to both the ad6620 and the by-pass latches. on the output of the ad6620, data is available in either serial or parallel mode. in serial mode, data may be sent directly to a dsp for system bread-boarding. in parallel mode, the data may be sent to the on-board fifo for spectral analysis by the included software. for additional information, refer to the evalua- tion board manual. filter design the ad6620 implements a pair of cascaded cic filters with a sum of products fir filter. the frequency characteristics of the cic filters have already been documented. additional reading on this class of filters can be found in an economical class of digital filters for decimation and interpolation, by eugene b. hogenauer, ieee transactions on acoustics, speech, and signal processing, volume assp-29, number 2, april 1981. the characteristics of the fir filter are fully programmable. the coefficie nts of this filter may be generated in any number of ways, using standard procedures such as parks-mcclellan. available software from analog devices that assists in the design of filters for this product. this software allows comparison between different distributions of decimation. the software works independently of the evaluation board, but easily allows transfer of design data directly to the evaluation board for immediate verification of the designed filter. the normal procedure for designing a filter for the chip is as shown in the flow chart. first, the desired characteristics must be determined based on the receive channel requirements. the decimation rates for the cic filters must then be selected such that their performance is near that of the desired channel require- ments. finally, an algorithm such as the parks-mcclellan or remez exchange is used to compute the final spectral require- ments, including droop correction for passband loss of the cic filters. if the designed filter meets the requirements, then the filter is acceptable. if not, another combination of cic filter decimation must be examined. tables iii and iv gr eatly simplify distribution and selection of cic requirements. the filter software available from analog devices helps to automate this procedure. select filter rejection requirements does cic2 filter protect enough bandwidth? select decimation rate for cic5 design rcf with remez exchange no yes select decimation rate for cic2 does cic5 filter protect enough bandwidth? does composite filter provide the desired results? yes no yes no figure 48. diagram of filter design software serial buffering the ad6620 serial outputs are designed to operate at very high speed. as such, care must be taken when driving the serial output lines. t hese high speed lines must be treated as transmission lines. critical lines include the sclk, sdfs, sdfe, sdi and sdo. it is recommended that these lines be series source termi- nated with the characteristic impedance of the driven line. if the lines are longer than a few inches, digital line buffers should be used as shown below. buffering in this manner will prevent reflections on the serial lines from disrupting operation of the ad6620. a good reference on transmission lines is found in the mecl system design handbook by motorola inc., s tock code hb205r1/d. ad6620 sclk sdo sdfs sclk sdo sdfs figure 49. serial line buffering and series source termination dsp/sharc interfacing with little effort, the ad6620 will interface to nearly all indus- try standard dsps, as shown in the figure below. the figures below show operation in tdm applications as well as in serial slave mode. in tdm mode the first ad6620 is configured to be the master. this chip is the first to access the serial data bus. when the master has data available in its output shifters, it generates an sdfs telling the dsp that serial data will follow. at this point,
ad6620 C39C rev. a the sdo of the master ad6620 takes control of the sdo line and begins shifting data out of the device. when all data has been shifted, the master raises the sdfe on the last shifted. this signals the next chip (slave) that on the next cycle of the clock it should take control of the sdo line and begin shifting data to the dsp. when the second ad6620 completes its shift, it raises its sdfe to signal the next chip in the chain, if present. if additional devices are connected to the chain, this would be used to indicate they should take control on the next clock cycle. this application does not have a third device and therefore, the frame would end. normally in an application with a single ad6620, the ad6620 would be configured as the serial bus master. however, there are applications where the dsp or other device may be the serial bus master. in this case, the diagram below illustrates how to configure the ad6620 so that it may be used in this mode. in order to use this in a meaningful application, the dsp must know when the ad6620 has new data available on its output. if the dsp polls the ad6620 too early, either old data will be present or the data could be in an indeterminate state. to prevent this, the ad6620 has an output pin dv out that signals the dsp when new data is available. this should be tied to an interrupt line of the dsp that is edge-sensitive, as the dv out line is only valid for two or four high speed clock cycles depending on the mode of the chip. the dsp may then invoke an interrupt service routine to handle the data, see text below. in this application, the dsp is responsible for generating the framing and clocking signals to the ad6620 as shown in figure 51. sclk ad6620 dsp +3.3v sbm sclk sdi dt sdo dr sdfs rfs sdfe 10k sdiv 2 4 ad wl 10k sclk sbm sdi sdo sdfs sdfe sdiv 2 4 ad wl ad6620 cascade figure 50. dual ad6620s using the serial bus in a tdm application sclk ad6620 dsp sclk sdi dt sdo dr sdfs rfs sdfe 10k sdiv 2 4 ad wl 10k sbm dv out irq figure 51. ad6620 configured as a serial slave software for single channel real operation when interfacing analog device s sharc dsp, the following code fragments can be used to configure the sharc. the first example shows how to configure the registers for use with a single channel application. the first segment of code defines the memory for use with the multichannel serial port data. the second segment of code sets up the serial port for receiving data only. it could have just as easily been set up for bidirectional data by properly setting the mtcsi register. the final two code segments are used when a serial port interrupt occurs. when the sharc detects completion of the serial port frame, an interrupt is generated and the final code segment is executed. the comments in that section show where user code should be inserted. the sharc takes care of moving the serial port buffers data directly to data memory as shown. / * * / / * multi-channel register setup * / .segment/dm dm_data; .var fm_demod_data[2]; / * array for receiving 1 real and imag sample * / .var fm_demod_tcb[8] = 0, 0, 0, 0, fm_demod_data+7, 2, 1, fm_demod_data; / * transfer control block for reception of fm d ata * / / * * / / * * / / * subroutine to setup sport1 for use with the ad6620 * / setup_sport1: r0 = 0; / * multi-channel enable setup * / dm(mtcs1) = r0; / * do not transmit on any channels * / r0 = 0; / * compand setup * / dm(mtccs1) = r0; / * no companding on transmit * / dm(mrccs1) = r0; / * no companding on receive * / r0 = 0x00100000; / * setup sport 1 transmit con trol register * / dm(stctl1) = r0; / * mfd = 1 * / r0 = 0x038c20f2; / * setup sport 1 receive control register * / dm(srctl1) = r0; / * slen = 15, sden & schen enabled * / / * sign extend, external sclk+rfs * / r0 = fm_demod_tcb + 7; / * tcb address * / dm(cp1) = r0; / * kickoff dma chain * / rts (db); / * return * / bit set imask spr1i; / * enable sport1 receive interrupt * / nop; / * * / spr1_svc: jump spr1_asserted; rti; rti; rti; / * * / / * * / / * process received data here. data samples located in fm_demod_data and fm_demod_data+1 spr1_asserted: push sts; / * push the status stack * / / * use secondary set of dags and register file * /
ad6620 C40C rev. a bit set mode1 srd1h | srd2l | srrfh | srrfl; nop; / * insert code here to process i and q data. the dsp serial port handler has placed the samples in fm_demod_data and fm_demod_data+1 * / pop sts; / * pop the status stack * / rti (db); / * switch back to primary set of dags and register file * / bit clr mode1 srd1h | srd2l | srrfh | srrfl; nop; .endseg; / * * / software for diversity channel real operation the code for interfacing to diversity channel real mode is very similar to that of single channel. the only difference being the number of channels allocated on the tdm chain. this process can easily be extended for any number of tdm channels as long as there is sufficient time in the frame to completely trans- mit the data. this procedure works with the appended data as well as serially cascaded devices. the code below demonstrates setup and operation in diversity channel mode. / * * / .segment/dm dm_data; / * multi-channel register setup * / .var fm_demod_data[4]; / * array for receiving 2 real and imag sample from each channel * / .var fm_demod_tcb[8] = 0, 0, 0, 0, 0, 4, 1, fm_demod_data; / * transfer control block for reception of fm data * / / * * / / * * / setup_sport1: r0 = 0; / * multi-channel enable setup * / dm(mtcs1) = r0; / * do not transmit on any channels * / r0 = 0; / * compand setup * / dm(mtccs1) = r0; / * no companding on transmit * / dm(mrccs1) = r0; / * no companding on receive * / r0 = 0x00100000; / * setup sport 1 transmit control register * / dm(stctl1) = r0; / * mfd = 1 * / r0 = 0x038c00f2; / * setup sport 1 re ceive control re gister * / dm(srctl1) = r0; / * slen = 15, sden & schen enabled * / / * sign extend, external sclk+rfs * / r0 = fm_demod_tcb + 7; / * tcb address * / dm(fm_demod_tcb + 4) = r0; / * tcb point back to itself * / dm(cp1) = r0; / * kickoff dma chain * / rts (db) / * return * / bit set imask spr1i; / * enable sport1 receive interrupt * / bit set imask cb15i; / * enable circular buffer 15 wrap interrupt for buffers full * / / * * / / * * / spr1_svc: jump spr1_asserted; rti; rti; rti; / * * / / * * / spr1_asserted: / * sport1 receive interrupt - do the fm demod and increment the counter * / push sts; / * push the status stack * / / * use secondary set of dags and register file * / bit set mode1 srd1h | srd1l | srd2h | srd2l | srrfh | srrfl; nop; / * insert code here for processing i and q data pairs. the dsp serial port handler has placed the samples in fm_demod_data through fm_demod_data+3 * / pop sts; / * pop the status stack * / rti (db); / * switch back to primary set of dags and register file * / bit clr mode1 srd1h | srd1l | srd2h | srd2l | srrfh | srrfl; nop; .endseg; / * * / typical latency expectations in the ad6620 latency can be divided into three components. for difficult filters, the largest component of latency is algorith- mic latency. this type of latency is tied inseparably to the de sired filter response. for smaller or minimal filters, fixed latency begins to dominate. this is the undesirable fixed delay associated with the calculation of the output samples. finally, variable latency, is the smallest component. this is the delay that can be influenced by the relative phase of internal decimated clocks with respect to the sync_cic. algorithmic latency is a necessary component of any filtering process be it analog or digital. since frequency is a variation with respect to time, it must take time to discriminate between analog frequencies. assuming the ad6620 is used to generate linear phase, low-pass filters, the algorithmic latency is a direct function of the number of rcf taps and the cic decimation ratios. in general, the largest part of the impulse response of these filters is the center of the impulse response length, so that the delay is represented by one-half the composite impulse response length. the impulse response length of the rcf is the number of taps times the rcf input sample period. therefore relative to the input sample clock the impulse response length of the rcf is given by; nmm f taps cic cic adc ? ( ) + 11 52 the impulse response length of the cic5 is given by; 55 1 52 ? ( ) + mm f cic cic adc
ad6620 C41C rev. a the impulse response length of the cic2 is given by 21 2 ? ( ) m f cic adc the composite impulse response length of all three stages is nmm mm m f taps cic cic cic cic cic adc +?+ 52 52 2 431 the algorithmic latency is nmm mm m f taps cic cic cic cic cic adc +?+ 52 52 2 431 2 fixed latency is the delay due to each register between the input and the output of the ad6620. the latency is the count of each register multiplied by the period of the clock that drives it. the fixed latency of the ad6620 can be approximated by the follow- ing expression: 10 7 7 5 25 tt m m m n t clk samp cic cic rcf taps clk ++ + + [] [] [] + where: t clk is the high speed clock to the ad6620. t samp is the data rate delivered to the ad6620. normally t clk and t samp are the same unless a clock multiplier is used such as with the ad6600 s 2 clock output. variable latency is due to any differences between the asyn- chronous edge of the sync pulses and the data rate. this includes use of the internal synchronization options. based on the information on latency, the plots shown below provide typical latency for a variety of different applications. they were obtained by inserting a f s dc step into the input data port of the ad6620. these are i channel step responses for the input transient. the latency is defined as the output period times number of output samples until the output reached approxi- mately 50% of the step value. output samples 0.20 0.40 1.00 121 3 fraction of f s 5791113151719 0.00 0.20 0.60 0.80 23 25 27 29 61.44mhz sample rate m cic2 = 16 m cic5 = 8 m rcf = 8 n taps = 256 at 19 output samples, the latency would be 0.32ms expected latency = 0.303ms figure 52. amps example output samples 0.20 0.40 111 2 fraction of f s 345678910 0.00 0.20 0.60 0.80 12 13 14 15 58.9824mhz sample rate m cic2 = 2 m cic5 = 4 m rcf = 6 n taps = 48 at 8 output samples, the latency would be 6.51 s expected latency = 6.31 s figure 53. cdma example output samples 0.20 0.40 121 3 fraction of f s 5791113151719 0.00 0.20 0.60 0.80 23 25 27 29 64.512mhz sample rate m cic2 = 2 m cic5 = 14 m rcf = 3 n taps = 84 at 19 output samples, the latency would be 24.7 s expected latency = 24.31 s figure 54. phs example output samples 0.20 0.40 111 2 fraction of f s 345678910 0.00 0.20 0.60 0.80 12 13 14 15 1.00 65.0mhz sample rate m cic2 = 2 m cic5 = 6 m rcf = 20 n taps = 240 at 9 output samples, the latency would be 33.23 s expected latency = 31.2 s #
33 (%.@),a
ad6620 C42C rev. a parallel processing using ad6620 if a single ad6620 does not have enough time to compute an adequate filter, multiple ad6620s can be operated in parallel as shown in figure 56. in this example, the processing is distrib- uted between four chips so that each chip can process more taps. the outputs are then combined such that the desired data rate is achieved. clk d in sync rcf d out dv out ad6620 #1 ain encode clock clk d in sync rcf d out dv out ad6620 #2 clk d in sync rcf d out dv out ad6620 #4 clk d in sync rcf d out dv out ad6620 #3 latch output selector rcf timing control ad6640 figure 56. parallel processing with the ad6620 in this application, one high speed adc can feed parallel ad6620s. although not shown in this diagram, the sync_nco and sync_cics are tied together and synchronized from an external source with all chips run as sync_slaves. this architecture allows for each ad6620 to process four times as many taps as would otherwise be possible. consider the example of an adc clocked at 58.9824 mhz and a desired output data rate of 4.9152 mhz. if a single ad6620 were used, the decimation rate would be 12 (58.9824/4.9152) allowing for only 12 taps in the fir filter. not nearly enough for a usable digital filter. now consider the case where each ad6620 only provides an output for one in four samples. in this case, the decimation rate per chip would be four times larger, 48 in this example. with a decimation of 48, more taps for the filter can be generated and produce a much better filter. counter 0 to 47 clock in count = 0 count = 11 count = 23 count = 35 figure 57. rcf timing generator for parallel processing implementation of such a procedure is quite simple and basi- cally shown in figure 57. the filter design would proceed by designing the filter to have the desired spectral charac teristics at its output rate. for our example here, each ad6620 would have an output rate of 1.2288 mhz. the filter should be designed such that the required rejection is attained directly at this rate. this one filter is loaded into each chip. upsampling is achieved on the output by multiplexing between the different ad6620 outputs which are staggered, in this case by 90 degrees of the output data rate. therefore, since the decimation rate is 48 and four ad6620s are used, every 12 high speed clock cycles a new ad6620 output should be selected. the most direct method is to use these pulses to trigger the sync_rcf signals. this staggering is required to properly phase the ad6620 s inter- nal computations. once the chips have been synchronized in this manner, they will begin producing dv out signals that can be used to instruct the output selector which output is valid. the rcf timing control is responsible for proper phasing of the ad6620s in the system. the example shown here is for the example of four devices in parallel. it can easily be expanded to any number of devices with this methodology. since the ad6620s are decimating by 48, the complete cycle time is 48 system clocks. thus the timing control must run modulo 48. when the count is 0, the first rcf should be reset with a pulse that is one clock cycle wide. likewise, when the count is 11, 23 and 35, rcf2, rcf3 and rcf4 should be reset respectively. this will properly phase the ad6620s to run 90 degrees out of phase. if this example consisted of six ad6620s, then they should be reset on count 0, 7, 15, 23, 31 and 39. following this method, any number of ad6620s can be paralleled for higher data rates. once the ad6620 rcfs are properly phased, the dv out signals will then enable the output selector to know which outputs should be connected at the correct point in time. in review, the dv out signal pulses high when the rcf data is being placed on the out- puts. since the devices are operated in single channel real mode, this signal will be high for two clock cycles while two pieces of data are written to the output. the output pairs consist of i followed by q. as each chip s dv out cycles high, its data should be connected to the output bus as shown below. this effectively forms a mux that sequentially cycles the output of each of the ad6620s in the system to the output port. the only remaining issue is retiming the data. since each ad6620 clocks its data out in two clock cycles, there will be 10 cycles where the data is idle. during this period, the last q out will remain valid until the next chip in the sequence generates its dv out signal. this normally should pose no problem, but if it does, the output data could easily go to a fifo and be retimed so that output data streams at a regular rate. in order to meet conventional logic requirements, oe for each of the input latches should be active low. the dv out of the ad6620 is active high, therefore, an inverter must be typically inserted between the dv out lines and the oe of the latches as shown in the updated figure 58.
ad6620 C43C rev. a clock dv out1 dv out2 dv out3 dv out4 ad6620 1 ad6620 2 ad6620 3 ad6620 4 selector output q i q iq i q i q i q i q i q i figure 59. timing for parallel processing oe input latching d out1 clock dv out1 d out2 clock dv out2 d out3 clock dv out3 d out4 clock dv out4 oe input latching oe input latching oe input latching output latching figure 58. parallel processing output selector in the output selector above each of the dv out lines is anded with main clock. this allows the data out of each of the ad6620s to be properly latched into the input latches. the dv out line is also responsible for placing the latched outputs on the internal bus at the proper time. this data is then latched in the output latch using the internal ored clocking signals. the timing for these events is shown in figure 59. as shown, the system clock is run at the specified rate. then the rcf timing control state machine is responsible for generating the appropriate sync pulses. when each ad6620 completes its sop computation, it generates the dv out pulses shown below. concur- rently, each chip places its iq data on the output pins of that device. with this data, the output selector state machine com- bines all of the data and places the data on the output bus. using the ad6620 in a narrow band system a typical interconnection between the ad6600, ad6620 and a general purpose dsp is shown in figure 65. this is an example of an if sampling narrow-band system and offers many techni- cal and cost advantages over traditional solutions. in this example, the ad6620 is in diversity channel real mode, with the ad 6600 sampling a diversity antenna on its b channel. the ad6620 performs floating-point to fixed-point conversion, digital tuning, digital filtering and decimation of the a/d output data. main input diversity input 2 clk a/b out 3 rssi bits 11 data bits encode sclk sdi sdo sdfs clk a/b e[2...0] in[15...5] ad6620 ad6600 sclk sdo sdi sdfs dsp figure 60. implementation of a narrow band receiver the 2 clk on the ad6600 is used as the processing clk of the ad6620. the use of this faster clock allows the rcf filter to process up to twice as many taps per sample. the increased number of taps available helps to improve the filter characteris- tics. in some applications an even faster processing clock may be necessary to allow for improved digital filter performance. in this case the a/b pin of the ad6620 must be toggled when each channel input is to be sampled. for most narrow-band uses of the ad6600/ad6620 combina- tion, a high oversampling ratio is desired. this spreads the quantization noise of the a/d over a wider spectrum and allows the digital filtering of the ad6620 to remove much of this noise. this effectively increases the snr of the ad6600. this process of oversampling and digital filtering is called process gain and its contribution to snr can be calculated from the equa- tion below. pg sample rate of channel signal bandwidth = ? ? ? ? ? ? 10 log ___ _ the process of oversampling can also provide the benefit of lowering the noise floor of the a/d. this can increase the effec- tive dynamic range of a receiver if the sampling rate is chosen such that the signal harmonics and/or intermodular distortion (imd) products fall out of the band of interest. in this case these spurs could be filtered by the ad6620 and the quantiza- tion noise would be the dominant dynamic range limitation of the ad6600/ad6620 receiver solution.
C44C c00967C0C6/01(a) printed in u.s.a. ad6620 rev. a a dsp is then used to perform the demodulation of the digital channel. this has the advantage of allowing for in-system con- figuration options and can even allow for improved modulation techniques to be applied in the future. this assumes that the ad6600 and the circuitry on its front end are compatible with the modulation standard to be used. for more information on using the ad6600 and ad6620 in a single carrier application, refer to analog devices application note an-502. using the ad6620 in a wideband system the ad6620 is fully capable of being utilized in a wide-band architecture system where a/ds such as the ad6640 or the ad9042 usually run at higher sample rates than those typically found in a narrow-band system. a correspondingly wider band can then be digitized. the digitization of this wide bandwidth allows many more channels to be digitized using the same a/d and if circuitry. the core configuration of such a system is shown in figure 61. the ad6640 and the ad6620 are both designed to run as fast as 67 mhz. in these applications the ad6620 will be used to process only one channel and will process the data at the a/d sample rate. additional channels can be processed by taking the ad6640 high speed data stream to additional ad6620s. each ad6620 can then be tuned to a different channel. the ad6620 provides a great deal of selectivity by mixing down a channel of interest as in the narrow-band case and filtering the out-of-band noise and adjacent channels. unlike the narrow- band solutions it is much more difficult to place the spurious content out of the band of interest because more of this band- width is used due to the larger number of carrier channels. the aliased spurs of one channel are likely to fold back on another 80-lead terminal plastic quad flatpack (pqfp) (s-80a) seating plane 0.134 (3.40) max 0.041 (1.03) 0.029 (0.73) 0.004 (0.10) max 0.120 (3.05) 0.100 (2.55) 0.010 (0.25) min 0.015 (0.38) 0.009 (0.22) 0.690 (17.45) 0.667 (16.95) 0.555 (14.10) 0.547 (13.90) 0.555 (14.10) 0.547 (13.90) 0.690 (17.45) 0.667 (16.95) 1 20 21 41 40 60 61 80 0.486 (12.35) bsc 0.486 (12.35) bsc top view (pins down) 0.026 (0.65) bsc outline dimensions dimensions shown in inches and (mm). clk d in ad6620 #1 serial i/o ain encode clock clk d in ad6620 #2 serial i/o clk d in ad6620 #3 serial i/o clk d in ad6620 #4 serial i/o dsp array latch ad6640 ad6644 figure 61. implementation of a multicarrier receiver channel. this places a greater requirement on the spurious free dynamic range (sfdr) of the a/d than in the narrow-band case. the sfdr is then usually the limiting factor of the wide- band system. provided that the a/d has sufficient sfdr for the air interface requirements, the ad6620 can use process gain, as in the narrow- band case, by filtering the out-of-band noise and adjacent channel power. this increases the snr of the digital data stream. as in the narrow-band system a dsp is then used to demodu- late the digital data. the same advantages of flexibility exist in the wide-band case as they did in the narrow-band case. future improvements in demodulation algorithms can be implemented in the receiver, provided that the front end hardware is compat- ible with the desired modulation standard.

▲Up To Search▲

Price & Availability of AD6620AS

	To Download AD6620AS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .